int_to_vector_suo.vo

来自「整型到字符型的转换」· VO 代码 · 共 851 行 · 第 1/2 页

defparam \input[7]~I .ddio_mode = "none";
defparam \input[7]~I .ddioinclk_input = "negated_inclk";
defparam \input[7]~I .dqs_delay_buffer_mode = "none";
defparam \input[7]~I .dqs_out_mode = "none";
defparam \input[7]~I .inclk_input = "normal";
defparam \input[7]~I .input_async_reset = "none";
defparam \input[7]~I .input_power_up = "low";
defparam \input[7]~I .input_register_mode = "none";
defparam \input[7]~I .input_sync_reset = "none";
defparam \input[7]~I .oe_async_reset = "none";
defparam \input[7]~I .oe_power_up = "low";
defparam \input[7]~I .oe_register_mode = "none";
defparam \input[7]~I .oe_sync_reset = "none";
defparam \input[7]~I .operation_mode = "input";
defparam \input[7]~I .output_async_reset = "none";
defparam \input[7]~I .output_power_up = "low";
defparam \input[7]~I .output_register_mode = "none";
defparam \input[7]~I .output_sync_reset = "none";
defparam \input[7]~I .sim_dqs_delay_increment = 0;
defparam \input[7]~I .sim_dqs_intrinsic_delay = 0;
defparam \input[7]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_R9
stratixii_io \q[0]~I (
	.datain(\input~combout [0]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(q[0]));
// synopsys translate_off
defparam \q[0]~I .ddio_mode = "none";
defparam \q[0]~I .ddioinclk_input = "negated_inclk";
defparam \q[0]~I .dqs_delay_buffer_mode = "none";
defparam \q[0]~I .dqs_out_mode = "none";
defparam \q[0]~I .inclk_input = "normal";
defparam \q[0]~I .input_async_reset = "none";
defparam \q[0]~I .input_power_up = "low";
defparam \q[0]~I .input_register_mode = "none";
defparam \q[0]~I .input_sync_reset = "none";
defparam \q[0]~I .oe_async_reset = "none";
defparam \q[0]~I .oe_power_up = "low";
defparam \q[0]~I .oe_register_mode = "none";
defparam \q[0]~I .oe_sync_reset = "none";
defparam \q[0]~I .operation_mode = "output";
defparam \q[0]~I .output_async_reset = "none";
defparam \q[0]~I .output_power_up = "low";
defparam \q[0]~I .output_register_mode = "none";
defparam \q[0]~I .output_sync_reset = "none";
defparam \q[0]~I .sim_dqs_delay_increment = 0;
defparam \q[0]~I .sim_dqs_intrinsic_delay = 0;
defparam \q[0]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_C15
stratixii_io \q[1]~I (
	.datain(\input~combout [1]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(q[1]));
// synopsys translate_off
defparam \q[1]~I .ddio_mode = "none";
defparam \q[1]~I .ddioinclk_input = "negated_inclk";
defparam \q[1]~I .dqs_delay_buffer_mode = "none";
defparam \q[1]~I .dqs_out_mode = "none";
defparam \q[1]~I .inclk_input = "normal";
defparam \q[1]~I .input_async_reset = "none";
defparam \q[1]~I .input_power_up = "low";
defparam \q[1]~I .input_register_mode = "none";
defparam \q[1]~I .input_sync_reset = "none";
defparam \q[1]~I .oe_async_reset = "none";
defparam \q[1]~I .oe_power_up = "low";
defparam \q[1]~I .oe_register_mode = "none";
defparam \q[1]~I .oe_sync_reset = "none";
defparam \q[1]~I .operation_mode = "output";
defparam \q[1]~I .output_async_reset = "none";
defparam \q[1]~I .output_power_up = "low";
defparam \q[1]~I .output_register_mode = "none";
defparam \q[1]~I .output_sync_reset = "none";
defparam \q[1]~I .sim_dqs_delay_increment = 0;
defparam \q[1]~I .sim_dqs_intrinsic_delay = 0;
defparam \q[1]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_W15
stratixii_io \q[2]~I (
	.datain(\input~combout [2]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(q[2]));
// synopsys translate_off
defparam \q[2]~I .ddio_mode = "none";
defparam \q[2]~I .ddioinclk_input = "negated_inclk";
defparam \q[2]~I .dqs_delay_buffer_mode = "none";
defparam \q[2]~I .dqs_out_mode = "none";
defparam \q[2]~I .inclk_input = "normal";
defparam \q[2]~I .input_async_reset = "none";
defparam \q[2]~I .input_power_up = "low";
defparam \q[2]~I .input_register_mode = "none";
defparam \q[2]~I .input_sync_reset = "none";
defparam \q[2]~I .oe_async_reset = "none";
defparam \q[2]~I .oe_power_up = "low";
defparam \q[2]~I .oe_register_mode = "none";
defparam \q[2]~I .oe_sync_reset = "none";
defparam \q[2]~I .operation_mode = "output";
defparam \q[2]~I .output_async_reset = "none";
defparam \q[2]~I .output_power_up = "low";
defparam \q[2]~I .output_register_mode = "none";
defparam \q[2]~I .output_sync_reset = "none";
defparam \q[2]~I .sim_dqs_delay_increment = 0;
defparam \q[2]~I .sim_dqs_intrinsic_delay = 0;
defparam \q[2]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_AA12
stratixii_io \q[3]~I (
	.datain(\input~combout [3]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(q[3]));
// synopsys translate_off
defparam \q[3]~I .ddio_mode = "none";
defparam \q[3]~I .ddioinclk_input = "negated_inclk";
defparam \q[3]~I .dqs_delay_buffer_mode = "none";
defparam \q[3]~I .dqs_out_mode = "none";
defparam \q[3]~I .inclk_input = "normal";
defparam \q[3]~I .input_async_reset = "none";
defparam \q[3]~I .input_power_up = "low";
defparam \q[3]~I .input_register_mode = "none";
defparam \q[3]~I .input_sync_reset = "none";
defparam \q[3]~I .oe_async_reset = "none";
defparam \q[3]~I .oe_power_up = "low";
defparam \q[3]~I .oe_register_mode = "none";
defparam \q[3]~I .oe_sync_reset = "none";
defparam \q[3]~I .operation_mode = "output";
defparam \q[3]~I .output_async_reset = "none";
defparam \q[3]~I .output_power_up = "low";
defparam \q[3]~I .output_register_mode = "none";
defparam \q[3]~I .output_sync_reset = "none";
defparam \q[3]~I .sim_dqs_delay_increment = 0;
defparam \q[3]~I .sim_dqs_intrinsic_delay = 0;
defparam \q[3]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_H1
stratixii_io \q[4]~I (
	.datain(\input~combout [4]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(q[4]));
// synopsys translate_off
defparam \q[4]~I .ddio_mode = "none";
defparam \q[4]~I .ddioinclk_input = "negated_inclk";
defparam \q[4]~I .dqs_delay_buffer_mode = "none";
defparam \q[4]~I .dqs_out_mode = "none";
defparam \q[4]~I .inclk_input = "normal";
defparam \q[4]~I .input_async_reset = "none";
defparam \q[4]~I .input_power_up = "low";
defparam \q[4]~I .input_register_mode = "none";
defparam \q[4]~I .input_sync_reset = "none";
defparam \q[4]~I .oe_async_reset = "none";
defparam \q[4]~I .oe_power_up = "low";
defparam \q[4]~I .oe_register_mode = "none";
defparam \q[4]~I .oe_sync_reset = "none";
defparam \q[4]~I .operation_mode = "output";
defparam \q[4]~I .output_async_reset = "none";
defparam \q[4]~I .output_power_up = "low";
defparam \q[4]~I .output_register_mode = "none";
defparam \q[4]~I .output_sync_reset = "none";
defparam \q[4]~I .sim_dqs_delay_increment = 0;
defparam \q[4]~I .sim_dqs_intrinsic_delay = 0;
defparam \q[4]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_W13
stratixii_io \q[5]~I (
	.datain(\input~combout [5]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(q[5]));
// synopsys translate_off
defparam \q[5]~I .ddio_mode = "none";
defparam \q[5]~I .ddioinclk_input = "negated_inclk";
defparam \q[5]~I .dqs_delay_buffer_mode = "none";
defparam \q[5]~I .dqs_out_mode = "none";
defparam \q[5]~I .inclk_input = "normal";
defparam \q[5]~I .input_async_reset = "none";
defparam \q[5]~I .input_power_up = "low";
defparam \q[5]~I .input_register_mode = "none";
defparam \q[5]~I .input_sync_reset = "none";
defparam \q[5]~I .oe_async_reset = "none";
defparam \q[5]~I .oe_power_up = "low";
defparam \q[5]~I .oe_register_mode = "none";
defparam \q[5]~I .oe_sync_reset = "none";
defparam \q[5]~I .operation_mode = "output";
defparam \q[5]~I .output_async_reset = "none";
defparam \q[5]~I .output_power_up = "low";
defparam \q[5]~I .output_register_mode = "none";
defparam \q[5]~I .output_sync_reset = "none";
defparam \q[5]~I .sim_dqs_delay_increment = 0;
defparam \q[5]~I .sim_dqs_intrinsic_delay = 0;
defparam \q[5]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_J2
stratixii_io \q[6]~I (
	.datain(\input~combout [6]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(q[6]));
// synopsys translate_off
defparam \q[6]~I .ddio_mode = "none";
defparam \q[6]~I .ddioinclk_input = "negated_inclk";
defparam \q[6]~I .dqs_delay_buffer_mode = "none";
defparam \q[6]~I .dqs_out_mode = "none";
defparam \q[6]~I .inclk_input = "normal";
defparam \q[6]~I .input_async_reset = "none";
defparam \q[6]~I .input_power_up = "low";
defparam \q[6]~I .input_register_mode = "none";
defparam \q[6]~I .input_sync_reset = "none";
defparam \q[6]~I .oe_async_reset = "none";
defparam \q[6]~I .oe_power_up = "low";
defparam \q[6]~I .oe_register_mode = "none";
defparam \q[6]~I .oe_sync_reset = "none";
defparam \q[6]~I .operation_mode = "output";
defparam \q[6]~I .output_async_reset = "none";
defparam \q[6]~I .output_power_up = "low";
defparam \q[6]~I .output_register_mode = "none";
defparam \q[6]~I .output_sync_reset = "none";
defparam \q[6]~I .sim_dqs_delay_increment = 0;
defparam \q[6]~I .sim_dqs_intrinsic_delay = 0;
defparam \q[6]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_B9
stratixii_io \q[7]~I (
	.datain(\input~combout [7]),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(q[7]));
// synopsys translate_off
defparam \q[7]~I .ddio_mode = "none";
defparam \q[7]~I .ddioinclk_input = "negated_inclk";
defparam \q[7]~I .dqs_delay_buffer_mode = "none";
defparam \q[7]~I .dqs_out_mode = "none";
defparam \q[7]~I .inclk_input = "normal";
defparam \q[7]~I .input_async_reset = "none";
defparam \q[7]~I .input_power_up = "low";
defparam \q[7]~I .input_register_mode = "none";
defparam \q[7]~I .input_sync_reset = "none";
defparam \q[7]~I .oe_async_reset = "none";
defparam \q[7]~I .oe_power_up = "low";
defparam \q[7]~I .oe_register_mode = "none";
defparam \q[7]~I .oe_sync_reset = "none";
defparam \q[7]~I .operation_mode = "output";
defparam \q[7]~I .output_async_reset = "none";
defparam \q[7]~I .output_power_up = "low";
defparam \q[7]~I .output_register_mode = "none";
defparam \q[7]~I .output_sync_reset = "none";
defparam \q[7]~I .sim_dqs_delay_increment = 0;
defparam \q[7]~I .sim_dqs_intrinsic_delay = 0;
defparam \q[7]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

endmodule