test_adder.v

64位乘法器

`timescale 1ns/1ns
module test_adder;

reg [1:0]sel;
reg clk;
reg rst;
reg [63:0] X,Y;

wire [64:0]sum;
wire [127:0]muilt_out;

parameter delay=20;

integer i;

always# (delay/2)
begin
  clk=~clk;
end

initial 
  begin
      clk=1;
      rst=0;
      #5 rst=1;
      X=64'b0;
      Y=64'b0;
      
  for (i=0;i<50;i=i+1)
     begin
      sel =$random%3;
      X[15:0]=$random%65535;
      X[31:16]=$random%65535;
      X[47:32]=$random%65535;
      X[63:48]=$random%65535;
      Y[15:0]=$random%65535;
      Y[31:16]=$random%65535;
      Y[47:32]=$random%65535;
      Y[63:48]=$random%65535;
     
     #60;
     end
  end
  
  sixty_adder m0(.X(X),.Y(Y),.sum(sum),.clk(clk),.rst(rst),.sel(sel),.muilt_out(muilt_out));
 endmodule