主程序备份.txt

64位乘法器

module sixty_adder(X,Y,sum,clk,rst,sel,muilt_out);
input [63:0] X,Y;
input  [1:0]sel;
input clk,rst;

output [64:0]sum;
output [127:0] muilt_out;

reg [63:0]X_reg,Y_reg ; 
reg [63:0]X_reg0,Y_reg0;
reg [63:0] X_reg1,Y_reg1;

reg [63:0] P,G; // P transfer carry,G bring carry
reg [63:0] P_sec; 
reg  P0_a,G0_a,P1_a,G1_a,P2_a,G2_a,P3_a,G3_a,P4_a,G4_a,P5_a,G5_a,P6_a,G6_a,P7_a,G7_a,P8_a,G8_a,P9_a,G9_a,
      P10_a,G10_a,P11_a,G11_a,P12_a,G12_a,P13_a,G13_a,P14_a,G14_a,P15_a,G15_a;
reg  P0_a_a,G0_a_a,P1_a_a,G1_a_a,P2_a_a,G2_a_a,P3_a_a,G3_a_a; 
reg  P0_a_a_a,G0_a_a_a;
reg  [63:0]CP;
reg  [64:0] sum;
 
reg [3:0]aid;

reg [63:0]part_tmp0;
reg [63:0]part_tmp1;
reg [63:0]part_tmp2;
reg [63:0]part_tmp3;

reg [15:0]Y_tmp0;
reg [15:0]Y_tmp1;
reg [15:0]Y_tmp2;
reg [15:0]Y_tmp3;

reg [79:0]part_out0;
reg [79:0]part_out1;
reg [79:0]part_out2;
reg [79:0]part_out3;

reg [96:0] part_adder0;
reg [96:0] part_adder1;

reg [127:0]muilt_out;

integer i,j,k,l;


//put the input X into Register X_reg
always@(posedge clk or negedge rst)
begin
if(!rst)
  X_reg<=64'b0;
else 
  X_reg<=X;
end

//put the input Y into Register Y_reg
always@(posedge clk or negedge rst)
begin
if(!rst)
  Y_reg<=64'b0;
else 
  Y_reg<=Y;
end



// select key this design can  realise low power
always@(X_reg or Y_reg or sel)
if (!rst)
begin
   X_reg0 <= 64'b0;
   Y_reg0 <= 64'b0;
   X_reg1 <= 64'b0;
   Y_reg1 <= 64'b0;
end
else
 begin
 case(sel)
     2'b00:  begin
                 X_reg0 <= X_reg;
                 Y_reg0 <= Y_reg;
                 X_reg1 <= 64'b0;
                 Y_reg1 <= 64'b0;
             end
     2'b01:  begin
                 X_reg0<=X_reg;
                 Y_reg0<=~Y_reg;
                 X_reg1<=64'b0;
                 Y_reg1<=64'b0;                 
             end
     2'b10:  begin
                 X_reg0<=64'b0;
                 Y_reg0<=64'b0;
                 X_reg1<=X_reg;
                 Y_reg1<=Y_reg;
             end
    default: begin
                 X_reg0<=64'b0;
                 Y_reg0<=64'b0;
                 X_reg1<=64'b0;
                 Y_reg1<=64'b0;
             end
endcase
end





//. cheng fa  mo kuai 
always @(Y_reg1[15:0] or X_reg1 or aid[0] or Y_tmp0 or part_tmp0 or i)

  begin
    for(i = 0 ; i <= 16 ; i = i + 1)
    begin
      if(i == 0)
      begin
          aid[0] = 0 ;
          part_tmp0 = 63'b0 ;
          Y_tmp0 = Y_reg1[15:0] ;
      end
      else
      begin
          case({Y_tmp0[0], aid[0]})
          2'b00:
          begin
               
              aid[0] = Y_tmp0[0] ; 
              Y_tmp0 = {part_tmp0[0], Y_tmp0[15 : 1]} ; 
              part_tmp0 = {part_tmp0[63], part_tmp0[63 : 1]} ;
          end
          2'b01:
          begin
              //A = A + M
              part_tmp0 = part_tmp0 + X_reg1;
              
              aid[0] = Y_tmp0[0] ; 
              Y_tmp0 = {part_tmp0[0], Y_tmp0[15 : 1]} ;
               part_tmp0 = {part_tmp0[63], part_tmp0[63 : 1]} ; 
          end
          2'b10:
          begin
              //A = A - M
              part_tmp0 = part_tmp0 + ~X_reg1+ 1'b1 ;
             
              aid[0] = Y_tmp0[0] ; 
              Y_tmp0 = {part_tmp0[0], Y_tmp0[15 : 1]} ;
               part_tmp0 = {part_tmp0[63], part_tmp0[63 : 1]} ;
          end
          2'b11:
          begin
              
              aid[0] = Y_tmp0[0] ; 
              Y_tmp0 = {part_tmp0[0], Y_tmp0[15 : 1]} ; 
              part_tmp0 = {part_tmp0[63], part_tmp0[63 : 1]} ; 
          end
          default:
          begin
              aid[0] = 1'b0 ;
              part_tmp0 = 64'b0 ;
              Y_tmp0 = 16'b0 ;
          end
        endcase
      end
       end
  end
    //Output register
  always @(posedge clk or negedge rst)
   begin
    if(!rst)
        part_out0<=79'b0 ;
    else if(Y_reg1[15:0] == 0 || X_reg1[63:0] == 0)
        part_out0 <=79'b0 ;
    else
        part_out0 <= {part_tmp0, Y_tmp0} ;
  end
  
  
 
 always @(Y_reg1[31:16] or X_reg1 or aid[1] or Y_tmp1 or part_tmp1 or j)

  begin
    for(j = 0 ; j <= 16 ; j= j+ 1)
    begin
      if(j == 0)
      begin
          aid[1] = 0 ;
          part_tmp1= 63'b0 ;
          Y_tmp1 = Y_reg1[31:16] ;
      end
      else
      begin
          case({Y_tmp1[0], aid[1]})
          2'b00:
          begin
               //Arithmetic shift
              aid[1] = Y_tmp1[0] ; 
              Y_tmp1 = {part_tmp1[0], Y_tmp1[15 : 1]} ; 
              part_tmp1= {part_tmp1[63], part_tmp1[63 : 1]} ;
          end
          2'b01:
          begin
              part_tmp1= part_tmp1+ X_reg1;
              //Arithmetic shift
              aid[1] = Y_tmp1[0] ; 
              Y_tmp1 = {part_tmp1[0], Y_tmp1[15 : 1]} ;
               part_tmp1= {part_tmp1[63], part_tmp1[63 : 1]} ; 
          end
          2'b10:
          begin
              //A = A - M
              part_tmp1= part_tmp1+ ~X_reg1+ 1'b1 ;
              //Arithmetic shift
              aid[1] = Y_tmp1[0] ; 
              Y_tmp1 = {part_tmp1[0], Y_tmp1[15 : 1]} ;
               part_tmp1= {part_tmp1[63], part_tmp1[63 : 1]} ;
          end
          2'b11:
          begin
              //Arithmetic shift
              aid[1] = Y_tmp1[0] ; 
              Y_tmp1 = {part_tmp1[0], Y_tmp1[15 : 1]} ; 
              part_tmp1= {part_tmp1[63], part_tmp1[63 : 1]} ; 
          end
          default:
          begin
              aid [1]= 1'b0 ;
              part_tmp1= 64'b0 ;
              Y_tmp1 = 16'b0 ;
          end
        endcase
        end
       end
  end
 

    //Output register
  always @(posedge clk or negedge rst)
   begin
    if(!rst)
        part_out1<=79'b0 ;
    else if(Y_reg1[31:16] == 0 || X_reg1[63:0] == 0)
        part_out1 <=79'b0 ;
    else
        part_out1 <= {part_tmp1, Y_tmp1} ;
  end
 
 
 

 always @(Y_reg1[47:32] or X_reg1 or aid[2] or Y_tmp2 or part_tmp2 or k)

  begin
    for(k = 0 ; k <= 16 ; k= k+ 1)
    begin
      if(k== 0)
      begin
          aid[2] = 0 ;
          part_tmp2= 63'b0 ;
          Y_tmp2 = Y_reg1[47:32] ;
      end
      else
      begin
          case({Y_tmp2[0], aid[2]})
          2'b00:
          begin
               //Arithmetic shift
              aid[2] = Y_tmp2[0] ; 
              Y_tmp2 = {part_tmp2[0], Y_tmp2[15 : 1]} ; 
              part_tmp2= {part_tmp2[63], part_tmp2[63 : 1]} ;
          end
          2'b01:
          begin
              //A = A + M
              part_tmp2= part_tmp2+ X_reg1;
              //Arithmetic shift
              aid[2] = Y_tmp2[0] ; 
              Y_tmp2 = {part_tmp2[0], Y_tmp2[15 : 1]} ;
               part_tmp2= {part_tmp2[63], part_tmp2[63 : 1]} ; 
          end
          2'b10:
          begin
              //A = A - M
              part_tmp2= part_tmp2+ ~X_reg1+ 1'b1 ;
              //Arithmetic shift
              aid[2] = Y_tmp2[0] ; 
              Y_tmp2 = {part_tmp2[0], Y_tmp2[15 : 1]} ;
               part_tmp2= {part_tmp2[63], part_tmp2[63 : 1]} ;
          end
          2'b11:
          begin
              //Arithmetic shift
              aid[2] = Y_tmp2[0] ; 
              Y_tmp2 = {part_tmp2[0], Y_tmp2[15 : 1]} ; 
              part_tmp2= {part_tmp2[63], part_tmp2[63 : 1]} ; 
          end
          default:
          begin
              aid [2]= 1'b0 ;
              part_tmp2= 64'b0 ;
              Y_tmp2 = 16'b0 ;
          end
        endcase
      end
       end
  end
 
     //Output register
  always @(posedge clk or negedge rst)
   begin
    if(!rst)
        part_out2<=79'b0 ;
    else if(Y_reg1[47:32] == 0 || X_reg1[63:0] == 0)
        part_out2 <=79'b0 ;
    else
        part_out2 <= {part_tmp2, Y_tmp2} ;
  end
 
 
 
 always @(Y_reg1[63:48] or X_reg1 or aid[3] or Y_tmp3 or part_tmp3 or l)

  begin
    for(l = 0 ; l <= 16 ;  l= l+ 1)
    begin
      if(l== 0)
      begin
          aid[3] = 0 ;
          part_tmp3= 63'b0 ;
          Y_tmp3 = Y_reg1[63:48] ;
      end
      else
      begin
          case({Y_tmp2[0], aid[3]})
          2'b00:
          begin
               //Arithmetic shift
              aid[3] = Y_tmp3[0] ; 
              Y_tmp3 = {part_tmp3[0], Y_tmp3[15 : 1]} ; 
              part_tmp3= {part_tmp3[63], part_tmp3[63 : 1]} ;
          end
          2'b01:
          begin
              //A = A + M
              part_tmp3= part_tmp3+ X_reg1;
              //Arithmetic shift
              aid[3] = Y_tmp3[0] ; 
              Y_tmp3 = {part_tmp3[0], Y_tmp3[15 : 1]} ;
               part_tmp3= {part_tmp3[63], part_tmp3[63 : 1]} ; 
          end
          2'b10:
          begin
              //A = A - M
              part_tmp3= part_tmp3+ ~X_reg1+ 1'b1 ;
              //Arithmetic shift
              aid[3] = Y_tmp3[0] ; 
              Y_tmp3 = {part_tmp3[0], Y_tmp3[15 : 1]} ;
               part_tmp3= {part_tmp3[63], part_tmp3[63 : 1]} ;
          end
          2'b11:
          begin
              //Arithmetic shift
              aid[3] = Y_tmp3[0] ; 
              Y_tmp3 = {part_tmp3[0], Y_tmp3[15 : 1]} ; 
              part_tmp3= {part_tmp3[63], part_tmp3[63 : 1]} ; 
          end
          default:
          begin
              aid [3]= 1'b0 ;
              part_tmp3= 64'b0 ;
              Y_tmp3 = 16'b0 ;
          end
        endcase
      end
       end
  end 
    //Output register
  always @(posedge clk or negedge rst)