shift.map.qmsg

移位寄存器,异步清零,异步置数,左移右移可控,具有循环移位功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 28 16:04:23 2007 " "Info: Processing started: Wed Nov 28 16:04:23 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shift -c shift " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shift -c shift" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shift.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shift-HL " "Info: Found design unit 1: shift-HL" {  } { { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 shift " "Info: Found entity 1: shift" {  } { { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "shift " "Info: Elaborating entity \"shift\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "c shift.vhd(14) " "Warning (10492): VHDL Process Statement warning at shift.vhd(14): signal \"c\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IOPT_MLS_CREATED_ALOAD_CCT" "" "Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." {  } { { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "23 " "Info: Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "12 " "Info: Implemented 12 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 28 16:04:25 2007 " "Info: Processing ended: Wed Nov 28 16:04:25 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}