shift.fit.qmsg

移位寄存器,异步清零,异步置数,左移右移可控,具有循环移位功能

{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.611 ns register register " "Info: Estimated most critical path is register to register delay of 2.611 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[2\]~975 1 REG LAB_X2_Y1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y1; Fanout = 1; REG Node = 'temp\[2\]~975'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "" { temp[2]~975 } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.206 ns) 0.881 ns temp\[2\]~976 2 COMB LAB_X2_Y1 3 " "Info: 2: + IC(0.675 ns) + CELL(0.206 ns) = 0.881 ns; Loc. = LAB_X2_Y1; Fanout = 3; COMB Node = 'temp\[2\]~976'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "0.881 ns" { temp[2]~975 temp[2]~976 } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 1.692 ns temp\[3\]~981 3 COMB LAB_X2_Y1 1 " "Info: 3: + IC(0.441 ns) + CELL(0.370 ns) = 1.692 ns; Loc. = LAB_X2_Y1; Fanout = 1; COMB Node = 'temp\[3\]~981'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "0.811 ns" { temp[2]~976 temp[3]~981 } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 2.503 ns temp\[3\]~982 4 COMB LAB_X2_Y1 1 " "Info: 4: + IC(0.605 ns) + CELL(0.206 ns) = 2.503 ns; Loc. = LAB_X2_Y1; Fanout = 1; COMB Node = 'temp\[3\]~982'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "0.811 ns" { temp[3]~981 temp[3]~982 } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.611 ns temp\[3\]~973 5 REG LAB_X2_Y1 1 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 2.611 ns; Loc. = LAB_X2_Y1; Fanout = 1; REG Node = 'temp\[3\]~973'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "0.108 ns" { temp[3]~982 temp[3]~973 } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 34.09 % ) " "Info: Total cell delay = 0.890 ns ( 34.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.721 ns ( 65.91 % ) " "Info: Total interconnect delay = 1.721 ns ( 65.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "2.611 ns" { temp[2]~975 temp[2]~976 temp[3]~981 temp[3]~982 temp[3]~973 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C5T144C8 " "Warning: Timing characteristics of device EP2C5T144C8 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "4 " "Warning: Found 4 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "q3 0 " "Warning: Pin \"q3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "q2 0 " "Warning: Pin \"q2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "q1 0 " "Warning: Pin \"q1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "q0 0 " "Warning: Pin \"q0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 28 16:04:29 2007 " "Info: Processing ended: Wed Nov 28 16:04:29 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}