count.tan.qmsg

模可变计数器,可实现模2模8模10模16,异步清零,模可变加减计数

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "cp register iq\[0\] register iq\[1\] 258.8 MHz 3.864 ns Internal " "Info: Clock \"cp\" has Internal fmax of 258.8 MHz between source register \"iq\[0\]\" and destination register \"iq\[1\]\" (period= 3.864 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iq\[0\] 1 REG LCFF_X2_Y4_N19 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y4_N19; Fanout = 8; REG Node = 'iq\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "" { iq[0] } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.496 ns) + CELL(0.624 ns) 1.120 ns iq\[2\]~2607 2 COMB LCCOMB_X2_Y4_N26 1 " "Info: 2: + IC(0.496 ns) + CELL(0.624 ns) = 1.120 ns; Loc. = LCCOMB_X2_Y4_N26; Fanout = 1; COMB Node = 'iq\[2\]~2607'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "1.120 ns" { iq[0] iq[2]~2607 } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.687 ns) + CELL(0.651 ns) 2.458 ns iq\[2\]~2609 3 COMB LCCOMB_X2_Y4_N2 2 " "Info: 3: + IC(0.687 ns) + CELL(0.651 ns) = 2.458 ns; Loc. = LCCOMB_X2_Y4_N2; Fanout = 2; COMB Node = 'iq\[2\]~2609'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "1.338 ns" { iq[2]~2607 iq[2]~2609 } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.624 ns) 3.492 ns iq~2611 4 COMB LCCOMB_X2_Y4_N20 1 " "Info: 4: + IC(0.410 ns) + CELL(0.624 ns) = 3.492 ns; Loc. = LCCOMB_X2_Y4_N20; Fanout = 1; COMB Node = 'iq~2611'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "1.034 ns" { iq[2]~2609 iq~2611 } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.600 ns iq\[1\] 5 REG LCFF_X2_Y4_N21 6 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 3.600 ns; Loc. = LCFF_X2_Y4_N21; Fanout = 6; REG Node = 'iq\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "0.108 ns" { iq~2611 iq[1] } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.007 ns ( 55.75 % ) " "Info: Total cell delay = 2.007 ns ( 55.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.593 ns ( 44.25 % ) " "Info: Total interconnect delay = 1.593 ns ( 44.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "3.600 ns" { iq[0] iq[2]~2607 iq[2]~2609 iq~2611 iq[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.600 ns" { iq[0] iq[2]~2607 iq[2]~2609 iq~2611 iq[1] } { 0.000ns 0.496ns 0.687ns 0.410ns 0.000ns } { 0.000ns 0.624ns 0.651ns 0.624ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.934 ns + Shortest register " "Info: + Shortest clock path from clock \"cp\" to destination register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 4 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "" { cp } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.334 ns) + CELL(0.666 ns) 2.934 ns iq\[1\] 2 REG LCFF_X2_Y4_N21 6 " "Info: 2: + IC(1.334 ns) + CELL(0.666 ns) = 2.934 ns; Loc. = LCFF_X2_Y4_N21; Fanout = 6; REG Node = 'iq\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.000 ns" { cp iq[1] } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.53 % ) " "Info: Total cell delay = 1.600 ns ( 54.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.334 ns ( 45.47 % ) " "Info: Total interconnect delay = 1.334 ns ( 45.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[1] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 2.934 ns - Longest register " "Info: - Longest clock path from clock \"cp\" to source register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 4 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "" { cp } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.334 ns) + CELL(0.666 ns) 2.934 ns iq\[0\] 2 REG LCFF_X2_Y4_N19 8 " "Info: 2: + IC(1.334 ns) + CELL(0.666 ns) = 2.934 ns; Loc. = LCFF_X2_Y4_N19; Fanout = 8; REG Node = 'iq\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.000 ns" { cp iq[0] } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.53 % ) " "Info: Total cell delay = 1.600 ns ( 54.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.334 ns ( 45.47 % ) " "Info: Total interconnect delay = 1.334 ns ( 45.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[0] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[1] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[0] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "3.600 ns" { iq[0] iq[2]~2607 iq[2]~2609 iq~2611 iq[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.600 ns" { iq[0] iq[2]~2607 iq[2]~2609 iq~2611 iq[1] } { 0.000ns 0.496ns 0.687ns 0.410ns 0.000ns } { 0.000ns 0.624ns 0.651ns 0.624ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[1] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[0] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "iq\[1\] d1 cp 6.872 ns register " "Info: tsu for register \"iq\[1\]\" (data pin = \"d1\", clock pin = \"cp\") is 6.872 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.846 ns + Longest pin register " "Info: + Longest pin to register delay is 9.846 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns d1 1 PIN PIN_42 3 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_42; Fanout = 3; PIN Node = 'd1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "" { d1 } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.782 ns) + CELL(0.650 ns) 7.366 ns iq\[2\]~2607 2 COMB LCCOMB_X2_Y4_N26 1 " "Info: 2: + IC(5.782 ns) + CELL(0.650 ns) = 7.366 ns; Loc. = LCCOMB_X2_Y4_N26; Fanout = 1; COMB Node = 'iq\[2\]~2607'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "6.432 ns" { d1 iq[2]~2607 } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.687 ns) + CELL(0.651 ns) 8.704 ns iq\[2\]~2609 3 COMB LCCOMB_X2_Y4_N2 2 " "Info: 3: + IC(0.687 ns) + CELL(0.651 ns) = 8.704 ns; Loc. = LCCOMB_X2_Y4_N2; Fanout = 2; COMB Node = 'iq\[2\]~2609'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "1.338 ns" { iq[2]~2607 iq[2]~2609 } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.624 ns) 9.738 ns iq~2611 4 COMB LCCOMB_X2_Y4_N20 1 " "Info: 4: + IC(0.410 ns) + CELL(0.624 ns) = 9.738 ns; Loc. = LCCOMB_X2_Y4_N20; Fanout = 1; COMB Node = 'iq~2611'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "1.034 ns" { iq[2]~2609 iq~2611 } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.846 ns iq\[1\] 5 REG LCFF_X2_Y4_N21 6 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 9.846 ns; Loc. = LCFF_X2_Y4_N21; Fanout = 6; REG Node = 'iq\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "0.108 ns" { iq~2611 iq[1] } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.967 ns ( 30.13 % ) " "Info: Total cell delay = 2.967 ns ( 30.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.879 ns ( 69.87 % ) " "Info: Total interconnect delay = 6.879 ns ( 69.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "9.846 ns" { d1 iq[2]~2607 iq[2]~2609 iq~2611 iq[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.846 ns" { d1 d1~combout iq[2]~2607 iq[2]~2609 iq~2611 iq[1] } { 0.000ns 0.000ns 5.782ns 0.687ns 0.410ns 0.000ns } { 0.000ns 0.934ns 0.650ns 0.651ns 0.624ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.934 ns - Shortest register " "Info: - Shortest clock path from clock \"cp\" to destination register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 4 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "" { cp } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.334 ns) + CELL(0.666 ns) 2.934 ns iq\[1\] 2 REG LCFF_X2_Y4_N21 6 " "Info: 2: + IC(1.334 ns) + CELL(0.666 ns) = 2.934 ns; Loc. = LCFF_X2_Y4_N21; Fanout = 6; REG Node = 'iq\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.000 ns" { cp iq[1] } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.53 % ) " "Info: Total cell delay = 1.600 ns ( 54.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.334 ns ( 45.47 % ) " "Info: Total interconnect delay = 1.334 ns ( 45.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[1] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "9.846 ns" { d1 iq[2]~2607 iq[2]~2609 iq~2611 iq[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.846 ns" { d1 d1~combout iq[2]~2607 iq[2]~2609 iq~2611 iq[1] } { 0.000ns 0.000ns 5.782ns 0.687ns 0.410ns 0.000ns } { 0.000ns 0.934ns 0.650ns 0.651ns 0.624ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[1] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cp q2 iq\[2\] 9.954 ns register " "Info: tco from clock \"cp\" to destination pin \"q2\" through register \"iq\[2\]\" is 9.954 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 2.934 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to source register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 4 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "" { cp } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.334 ns) + CELL(0.666 ns) 2.934 ns iq\[2\] 2 REG LCFF_X2_Y4_N31 5 " "Info: 2: + IC(1.334 ns) + CELL(0.666 ns) = 2.934 ns; Loc. = LCFF_X2_Y4_N31; Fanout = 5; REG Node = 'iq\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.000 ns" { cp iq[2] } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.53 % ) " "Info: Total cell delay = 1.600 ns ( 54.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.334 ns ( 45.47 % ) " "Info: Total interconnect delay = 1.334 ns ( 45.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[2] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.716 ns + Longest register pin " "Info: + Longest register to pin delay is 6.716 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iq\[2\] 1 REG LCFF_X2_Y4_N31 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y4_N31; Fanout = 5; REG Node = 'iq\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "" { iq[2] } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.680 ns) + CELL(3.036 ns) 6.716 ns q2 2 PIN PIN_92 0 " "Info: 2: + IC(3.680 ns) + CELL(3.036 ns) = 6.716 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'q2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "6.716 ns" { iq[2] q2 } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.036 ns ( 45.21 % ) " "Info: Total cell delay = 3.036 ns ( 45.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.680 ns ( 54.79 % ) " "Info: Total interconnect delay = 3.680 ns ( 54.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "6.716 ns" { iq[2] q2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.716 ns" { iq[2] q2 } { 0.000ns 3.680ns } { 0.000ns 3.036ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[2] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "6.716 ns" { iq[2] q2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.716 ns" { iq[2] q2 } { 0.000ns 3.680ns } { 0.000ns 3.036ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "iq\[3\] en cp -4.517 ns register " "Info: th for register \"iq\[3\]\" (data pin = \"en\", clock pin = \"cp\") is -4.517 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.934 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to destination register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 4 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "" { cp } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.334 ns) + CELL(0.666 ns) 2.934 ns iq\[3\] 2 REG LCFF_X2_Y4_N7 3 " "Info: 2: + IC(1.334 ns) + CELL(0.666 ns) = 2.934 ns; Loc. = LCFF_X2_Y4_N7; Fanout = 3; REG Node = 'iq\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.000 ns" { cp iq[3] } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.53 % ) " "Info: Total cell delay = 1.600 ns ( 54.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.334 ns ( 45.47 % ) " "Info: Total interconnect delay = 1.334 ns ( 45.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[3] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.757 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.757 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns en 1 PIN PIN_26 4 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_26; Fanout = 4; PIN Node = 'en'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "" { en } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.967 ns) + CELL(0.855 ns) 7.757 ns iq\[3\] 2 REG LCFF_X2_Y4_N7 3 " "Info: 2: + IC(5.967 ns) + CELL(0.855 ns) = 7.757 ns; Loc. = LCFF_X2_Y4_N7; Fanout = 3; REG Node = 'iq\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "6.822 ns" { en iq[3] } "NODE_NAME" } "" } } { "count.vhd" "" { Text "D:/count/count.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.790 ns ( 23.08 % ) " "Info: Total cell delay = 1.790 ns ( 23.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.967 ns ( 76.92 % ) " "Info: Total interconnect delay = 5.967 ns ( 76.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "7.757 ns" { en iq[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.757 ns" { en en~combout iq[3] } { 0.000ns 0.000ns 5.967ns } { 0.000ns 0.935ns 0.855ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "2.934 ns" { cp iq[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.934 ns" { cp cp~combout iq[3] } { 0.000ns 0.000ns 1.334ns } { 0.000ns 0.934ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "count" "UNKNOWN" "V1" "D:/count/db/count.quartus_db" { Floorplan "D:/count/" "" "7.757 ns" { en iq[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.757 ns" { en en~combout iq[3] } { 0.000ns 0.000ns 5.967ns } { 0.000ns 0.935ns 0.855ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}