count.vhd

来自「模可变计数器,可实现模2模8模10模16,异步清零,模可变加减计数」· VHDL 代码 · 共 78 行

 library ieee;
 use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity count is
port(en,c,cp,u,d1,d0:in std_logic;
     q3,q2,q1,q0:out std_logic);
end count;
architecture behave of count is
signal iq:unsigned(3 downto 0);
begin
q3<=iq(3);q2<=iq(2);q1<=iq(1);
q0<=iq(0);
process(en,cp,c,u,d1,d0)
begin
if(c='0')then
      iq<=(others=>'0');
   elsif(cp'event and cp='1')then
  
    if(en='1')then
    if(d1='0'and d0='0')then
     if(u='0')then
      if(iq=1)then
	iq<="0000";
    else iq<=iq+1;
      end if;
    elsif(u='1')then
    if(iq=0)then
     iq<="0001";
      else iq<=iq+1;
     end if;
    end if;
   elsif(d1='0'and d0='1')then
     if(u='0')then
      if(iq=7)then
	iq<="0000";
    else iq<=iq+1;
      end if;
    elsif(u='1')then
    if(iq=0)then
     iq<="0111";
      else iq<=iq+1;
     end if;
    end if;
     elsif(d1='1'and d0='0')then
     if(u='0')then
      if(iq=9)then
	iq<="0000";
    else iq<=iq+1;
      end if;
    elsif(u='1')then
    if(iq=0)then
     iq<="1001";
      else iq<=iq+1;
     end if;
    end if;
     elsif(d1='1'and d0='1')then
     if(u='0')then
      if(iq=15)then
	iq<="0000";
    else iq<=iq+1;
      end if;
    elsif(u='1')then
    if(iq=0)then
     iq<="1111";
      else iq<=iq+1;
     end if;
    end if;
  end if;
 end if;
end if;
end process;
end behave;