chk1101.map.qmsg

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 02 22:30:45 2007 " "Info: Processing started: Sun Dec 02 22:30:45 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chk1101 -c chk1101 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chk1101 -c chk1101" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chk1101.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file chk1101.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 chk1101-rtl " "Info: Found design unit 1: chk1101-rtl" {  } { { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 chk1101 " "Info: Found entity 1: chk1101" {  } { { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "chk1101 " "Info: Elaborating entity \"chk1101\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "en chk1101.vhd(18) " "Warning (10492): VHDL Process Statement warning at chk1101.vhd(18): signal \"en\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "d chk1101.vhd(16) " "Warning (10631): VHDL Process Statement warning at chk1101.vhd(16): signal or variable \"d\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"d\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "10 " "Info: Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "3 " "Info: Implemented 3 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 02 22:30:46 2007 " "Info: Processing ended: Sun Dec 02 22:30:46 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}