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📄 chk1101.tan.qmsg

📁 序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器
💻 QMSG
📖 第 1 页 / 共 3 页
字号:
🔍
123 
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register F r~reg0 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"F\" and destination register \"r~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.747 ns + Longest register register " "Info: + Longest register to register delay is 0.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns F 1 REG LCFF_X1_Y13_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'F'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "" { F } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.206 ns) 0.639 ns r~204 2 COMB LCCOMB_X1_Y13_N20 1 " "Info: 2: + IC(0.433 ns) + CELL(0.206 ns) = 0.639 ns; Loc. = LCCOMB_X1_Y13_N20; Fanout = 1; COMB Node = 'r~204'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.639 ns" { F r~204 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.747 ns r~reg0 3 REG LCFF_X1_Y13_N21 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.747 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.108 ns" { r~204 r~reg0 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 42.03 % ) " "Info: Total cell delay = 0.314 ns ( 42.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.433 ns ( 57.97 % ) " "Info: Total interconnect delay = 0.433 ns ( 57.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.747 ns" { F r~204 r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "0.747 ns" { F r~204 r~reg0 } { 0.000ns 0.433ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.744 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "" { clk } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns clk~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.666 ns) 2.744 ns r~reg0 3 REG LCFF_X1_Y13_N21 2 " "Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.744 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "1.511 ns" { clk~clkctrl r~reg0 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.99 % ) " "Info: Total cell delay = 1.756 ns ( 63.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.988 ns ( 36.01 % ) " "Info: Total interconnect delay = 0.988 ns ( 36.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl r~reg0 } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.744 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "" { clk } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns clk~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.666 ns) 2.744 ns F 3 REG LCFF_X1_Y13_N1 2 " "Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.744 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'F'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "1.511 ns" { clk~clkctrl F } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.99 % ) " "Info: Total cell delay = 1.756 ns ( 63.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.988 ns ( 36.01 % ) " "Info: Total interconnect delay = 0.988 ns ( 36.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl F } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl F } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl r~reg0 } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl F } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl F } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.747 ns" { F r~204 r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "0.747 ns" { F r~204 r~reg0 } { 0.000ns 0.433ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl r~reg0 } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl F } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl F } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "" { r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { r~reg0 } {  } {  } } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "F din\[0\] clk 5.919 ns register " "Info: tsu for register \"F\" (data pin = \"din\[0\]\", clock pin = \"clk\") is 5.919 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.703 ns + Longest pin register " "Info: + Longest pin to register delay is 8.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns din\[0\] 1 PIN PIN_136 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_136; Fanout = 1; PIN Node = 'din\[0\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "" { din[0] } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.041 ns) + CELL(0.623 ns) 7.598 ns r~203 2 COMB LCCOMB_X1_Y13_N18 2 " "Info: 2: + IC(6.041 ns) + CELL(0.623 ns) = 7.598 ns; Loc. = LCCOMB_X1_Y13_N18; Fanout = 2; COMB Node = 'r~203'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "6.664 ns" { din[0] r~203 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.624 ns) 8.595 ns F~44 3 COMB LCCOMB_X1_Y13_N0 1 " "Info: 3: + IC(0.373 ns) + CELL(0.624 ns) = 8.595 ns; Loc. = LCCOMB_X1_Y13_N0; Fanout = 1; COMB Node = 'F~44'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.997 ns" { r~203 F~44 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.703 ns F 4 REG LCFF_X1_Y13_N1 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.703 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'F'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.108 ns" { F~44 F } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.289 ns ( 26.30 % ) " "Info: Total cell delay = 2.289 ns ( 26.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.414 ns ( 73.70 % ) " "Info: Total interconnect delay = 6.414 ns ( 73.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "8.703 ns" { din[0] r~203 F~44 F } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "8.703 ns" { din[0] din[0]~combout r~203 F~44 F } { 0.000ns 0.000ns 6.041ns 0.373ns 0.000ns } { 0.000ns 0.934ns 0.623ns 0.624ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.744 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "" { clk } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns clk~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.666 ns) 2.744 ns F 3 REG LCFF_X1_Y13_N1 2 " "Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.744 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'F'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "1.511 ns" { clk~clkctrl F } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.99 % ) " "Info: Total cell delay = 1.756 ns ( 63.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.988 ns ( 36.01 % ) " "Info: Total interconnect delay = 0.988 ns ( 36.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl F } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl F } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "8.703 ns" { din[0] r~203 F~44 F } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "8.703 ns" { din[0] din[0]~combout r~203 F~44 F } { 0.000ns 0.000ns 6.041ns 0.373ns 0.000ns } { 0.000ns 0.934ns 0.623ns 0.624ns 0.108ns } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl F } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl F } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk r r~reg0 6.808 ns register " "Info: tco from clock \"clk\" to destination pin \"r\" through register \"r~reg0\" is 6.808 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.744 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "" { clk } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns clk~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.666 ns) 2.744 ns r~reg0 3 REG LCFF_X1_Y13_N21 2 " "Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.744 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "1.511 ns" { clk~clkctrl r~reg0 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.99 % ) " "Info: Total cell delay = 1.756 ns ( 63.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.988 ns ( 36.01 % ) " "Info: Total interconnect delay = 0.988 ns ( 36.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl r~reg0 } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.760 ns + Longest register pin " "Info: + Longest register to pin delay is 3.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns r~reg0 1 REG LCFF_X1_Y13_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "" { r~reg0 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.704 ns) + CELL(3.056 ns) 3.760 ns r 2 PIN PIN_4 0 " "Info: 2: + IC(0.704 ns) + CELL(3.056 ns) = 3.760 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'r'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "3.760 ns" { r~reg0 r } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.056 ns ( 81.28 % ) " "Info: Total cell delay = 3.056 ns ( 81.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.704 ns ( 18.72 % ) " "Info: Total interconnect delay = 0.704 ns ( 18.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "3.760 ns" { r~reg0 r } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.760 ns" { r~reg0 r } { 0.000ns 0.704ns } { 0.000ns 3.056ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl r~reg0 } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "3.760 ns" { r~reg0 r } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.760 ns" { r~reg0 r } { 0.000ns 0.704ns } { 0.000ns 3.056ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "r~reg0 din\[1\] clk -0.839 ns register " "Info: th for register \"r~reg0\" (data pin = \"din\[1\]\", clock pin = \"clk\") is -0.839 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.744 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "" { clk } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns clk~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.666 ns) 2.744 ns r~reg0 3 REG LCFF_X1_Y13_N21 2 " "Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.744 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "1.511 ns" { clk~clkctrl r~reg0 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.99 % ) " "Info: Total cell delay = 1.756 ns ( 63.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.988 ns ( 36.01 % ) " "Info: Total interconnect delay = 0.988 ns ( 36.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl r~reg0 } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.889 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.889 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns din\[1\] 1 PIN PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; PIN Node = 'din\[1\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "" { din[1] } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.330 ns) + CELL(0.370 ns) 2.790 ns r~203 2 COMB LCCOMB_X1_Y13_N18 2 " "Info: 2: + IC(1.330 ns) + CELL(0.370 ns) = 2.790 ns; Loc. = LCCOMB_X1_Y13_N18; Fanout = 2; COMB Node = 'r~203'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "1.700 ns" { din[1] r~203 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.367 ns) + CELL(0.624 ns) 3.781 ns r~204 3 COMB LCCOMB_X1_Y13_N20 1 " "Info: 3: + IC(0.367 ns) + CELL(0.624 ns) = 3.781 ns; Loc. = LCCOMB_X1_Y13_N20; Fanout = 1; COMB Node = 'r~204'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.991 ns" { r~203 r~204 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.889 ns r~reg0 4 REG LCFF_X1_Y13_N21 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 3.889 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "0.108 ns" { r~204 r~reg0 } "NODE_NAME" } "" } } { "chk1101.vhd" "" { Text "E:/Program Files/altera/shong/chk1101/chk1101.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.192 ns ( 56.36 % ) " "Info: Total cell delay = 2.192 ns ( 56.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.697 ns ( 43.64 % ) " "Info: Total interconnect delay = 1.697 ns ( 43.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "3.889 ns" { din[1] r~203 r~204 r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.889 ns" { din[1] din[1]~combout r~203 r~204 r~reg0 } { 0.000ns 0.000ns 1.330ns 0.367ns 0.000ns } { 0.000ns 1.090ns 0.370ns 0.624ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "2.744 ns" { clk clk~clkctrl r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "2.744 ns" { clk clk~combout clk~clkctrl r~reg0 } { 0.000ns 0.000ns 0.143ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "chk1101" "UNKNOWN" "V1" "E:/Program Files/altera/shong/chk1101/db/chk1101.quartus_db" { Floorplan "E:/Program Files/altera/shong/chk1101/" "" "3.889 ns" { din[1] r~203 r~204 r~reg0 } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.889 ns" { din[1] din[1]~combout r~203 r~204 r~reg0 } { 0.000ns 0.000ns 1.330ns 0.367ns 0.000ns } { 0.000ns 1.090ns 0.370ns 0.624ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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