📄 chk1101.fit.eqn
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-- Copyright (C) 1991-2006 Altera Corporation
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-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
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-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
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--A1L14Q is r~reg0 at LCFF_X1_Y13_N21
A1L14Q = DFFEAS(A1L13, GLOBAL(A1L2), , , , , , , );
--F is F at LCFF_X1_Y13_N1
F = DFFEAS(A1L10, GLOBAL(A1L2), , , , , , , );
--A1L12 is r~203 at LCCOMB_X1_Y13_N18
A1L12 = din[2] & din[0] & !din[1] # !din[2] & (din[1] & din[3]);
--A1L13 is r~204 at LCCOMB_X1_Y13_N20
A1L13 = en & (A1L14Q) # !en & (A1L12 & A1L14Q # !A1L12 & (F));
--A1L10 is F~44 at LCCOMB_X1_Y13_N0
A1L10 = en & (F) # !en & A1L12;
--en is en at PIN_141
--operation mode is input
en = INPUT();
--din[0] is din[0] at PIN_136
--operation mode is input
din[0] = INPUT();
--din[3] is din[3] at PIN_3
--operation mode is input
din[3] = INPUT();
--din[1] is din[1] at PIN_18
--operation mode is input
din[1] = INPUT();
--din[2] is din[2] at PIN_21
--operation mode is input
din[2] = INPUT();
--clk is clk at PIN_17
--operation mode is input
clk = INPUT();
--r is r at PIN_4
--operation mode is output
r = OUTPUT(A1L14Q);
--A1L2 is clk~clkctrl at CLKCTRL_G2
A1L2 = cycloneii_clkctrl(.INCLK[0] = clk) WITH (clock_type = "Global Clock");
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