chk1101.map.rpt

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; -1                 ; -1                 ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                   ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                      ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------+
; chk1101.vhd                      ; yes             ; User VHDL File  ; E:/Program Files/altera/shong/chk1101/chk1101.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+---------------------------------------------+--------+
; Resource                                    ; Usage  ;
+---------------------------------------------+--------+
; Total combinational functions               ; 3      ;
; Logic element usage by number of LUT inputs ;        ;
;     -- 4 input functions                    ; 2      ;
;     -- 3 input functions                    ; 1      ;
;     -- <=2 input functions                  ; 0      ;
;         -- Combinational cells for routing  ; 0      ;
; Logic elements by mode                      ;        ;
;     -- normal mode                          ; 3      ;
;     -- arithmetic mode                      ; 0      ;
; Total registers                             ; 2      ;
; I/O pins                                    ; 7      ;
; Maximum fan-out node                        ; r~reg0 ;
; Maximum fan-out                             ; 2      ;
; Total fan-out                               ; 16     ;
; Average fan-out                             ; 1.33   ;
+---------------------------------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |chk1101                   ; 3 (3)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 7    ; 0            ; |chk1101            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 2     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Program Files/altera/shong/chk1101/chk1101.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Dec 02 22:30:45 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chk1101 -c chk1101
Info: Found 2 design units, including 1 entities, in source file chk1101.vhd
    Info: Found design unit 1: chk1101-rtl
    Info: Found entity 1: chk1101
Info: Elaborating entity "chk1101" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at chk1101.vhd(18): signal "en" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at chk1101.vhd(16): signal or variable "d" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "d" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Implemented 10 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 1 output pins
    Info: Implemented 3 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun Dec 02 22:30:46 2007
    Info: Elapsed time: 00:00:02