chk1101.tan.rpt

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

+-------+--------------+------------+--------+--------+----------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From   ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A   ; None         ; 6.808 ns   ; r~reg0 ; r  ; clk        ;
+-------+--------------+------------+--------+----+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+--------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To     ; To Clock ;
+---------------+-------------+-----------+--------+--------+----------+
; N/A           ; None        ; -0.839 ns ; din[1] ; r~reg0 ; clk      ;
; N/A           ; None        ; -0.845 ns ; din[1] ; F      ; clk      ;
; N/A           ; None        ; -1.129 ns ; din[2] ; r~reg0 ; clk      ;
; N/A           ; None        ; -1.135 ns ; din[2] ; F      ; clk      ;
; N/A           ; None        ; -3.920 ns ; en     ; F      ; clk      ;
; N/A           ; None        ; -4.399 ns ; en     ; r~reg0 ; clk      ;
; N/A           ; None        ; -4.457 ns ; din[3] ; r~reg0 ; clk      ;
; N/A           ; None        ; -4.463 ns ; din[3] ; F      ; clk      ;
; N/A           ; None        ; -5.647 ns ; din[0] ; r~reg0 ; clk      ;
; N/A           ; None        ; -5.653 ns ; din[0] ; F      ; clk      ;
+---------------+-------------+-----------+--------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Dec 02 22:30:53 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off chk1101 -c chk1101 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "F" and destination register "r~reg0"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.747 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'F'
            Info: 2: + IC(0.433 ns) + CELL(0.206 ns) = 0.639 ns; Loc. = LCCOMB_X1_Y13_N20; Fanout = 1; COMB Node = 'r~204'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.747 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'
            Info: Total cell delay = 0.314 ns ( 42.03 % )
            Info: Total interconnect delay = 0.433 ns ( 57.97 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.744 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.744 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'
                Info: Total cell delay = 1.756 ns ( 63.99 % )
                Info: Total interconnect delay = 0.988 ns ( 36.01 % )
            Info: - Longest clock path from clock "clk" to source register is 2.744 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.744 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'F'
                Info: Total cell delay = 1.756 ns ( 63.99 % )
                Info: Total interconnect delay = 0.988 ns ( 36.01 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "F" (data pin = "din[0]", clock pin = "clk") is 5.919 ns
    Info: + Longest pin to register delay is 8.703 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_136; Fanout = 1; PIN Node = 'din[0]'
        Info: 2: + IC(6.041 ns) + CELL(0.623 ns) = 7.598 ns; Loc. = LCCOMB_X1_Y13_N18; Fanout = 2; COMB Node = 'r~203'
        Info: 3: + IC(0.373 ns) + CELL(0.624 ns) = 8.595 ns; Loc. = LCCOMB_X1_Y13_N0; Fanout = 1; COMB Node = 'F~44'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.703 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'F'
        Info: Total cell delay = 2.289 ns ( 26.30 % )
        Info: Total interconnect delay = 6.414 ns ( 73.70 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.744 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.744 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'F'
        Info: Total cell delay = 1.756 ns ( 63.99 % )
        Info: Total interconnect delay = 0.988 ns ( 36.01 % )
Info: tco from clock "clk" to destination pin "r" through register "r~reg0" is 6.808 ns
    Info: + Longest clock path from clock "clk" to source register is 2.744 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.744 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'
        Info: Total cell delay = 1.756 ns ( 63.99 % )
        Info: Total interconnect delay = 0.988 ns ( 36.01 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 3.760 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'
        Info: 2: + IC(0.704 ns) + CELL(3.056 ns) = 3.760 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'r'
        Info: Total cell delay = 3.056 ns ( 81.28 % )
        Info: Total interconnect delay = 0.704 ns ( 18.72 % )
Info: th for register "r~reg0" (data pin = "din[1]", clock pin = "clk") is -0.839 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.744 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.744 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'
        Info: Total cell delay = 1.756 ns ( 63.99 % )
        Info: Total interconnect delay = 0.988 ns ( 36.01 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 3.889 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; PIN Node = 'din[1]'
        Info: 2: + IC(1.330 ns) + CELL(0.370 ns) = 2.790 ns; Loc. = LCCOMB_X1_Y13_N18; Fanout = 2; COMB Node = 'r~203'
        Info: 3: + IC(0.367 ns) + CELL(0.624 ns) = 3.781 ns; Loc. = LCCOMB_X1_Y13_N20; Fanout = 1; COMB Node = 'r~204'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 3.889 ns; Loc. = LCFF_X1_Y13_N21; Fanout = 2; REG Node = 'r~reg0'
        Info: Total cell delay = 2.192 ns ( 56.36 % )
        Info: Total interconnect delay = 1.697 ns ( 43.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Dec 02 22:30:53 2007
    Info: Elapsed time: 00:00:00