schk.tan.rpt

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

; Slack ; Required tsu ; Actual tsu ; From ; To   ; To Clock ;
+-------+--------------+------------+------+------+----------+
; N/A   ; None         ; 6.009 ns   ; din  ; Q[0] ; clk      ;
; N/A   ; None         ; 5.724 ns   ; din  ; Q[4] ; clk      ;
; N/A   ; None         ; 5.694 ns   ; din  ; Q[2] ; clk      ;
; N/A   ; None         ; 5.636 ns   ; din  ; Q[3] ; clk      ;
; N/A   ; None         ; 5.520 ns   ; din  ; Q[1] ; clk      ;
+-------+--------------+------------+------+------+----------+


+------------------------------------------------------------+
; tco                                                        ;
+-------+--------------+------------+------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+----+------------+
; N/A   ; None         ; 9.085 ns   ; Q[0] ; F  ; clk        ;
; N/A   ; None         ; 9.051 ns   ; Q[4] ; F  ; clk        ;
; N/A   ; None         ; 8.905 ns   ; Q[3] ; F  ; clk        ;
; N/A   ; None         ; 8.603 ns   ; Q[2] ; F  ; clk        ;
; N/A   ; None         ; 8.266 ns   ; Q[1] ; F  ; clk        ;
+-------+--------------+------------+------+----+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; -4.949 ns ; din  ; Q[2] ; clk      ;
; N/A           ; None        ; -4.979 ns ; din  ; Q[4] ; clk      ;
; N/A           ; None        ; -4.985 ns ; din  ; Q[3] ; clk      ;
; N/A           ; None        ; -5.254 ns ; din  ; Q[1] ; clk      ;
; N/A           ; None        ; -5.292 ns ; din  ; Q[0] ; clk      ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Dec 05 15:34:20 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off schk -c schk --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "Q[3]" and destination register "Q[1]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.393 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X6_Y13_N5; Fanout = 7; REG Node = 'Q[3]'
            Info: 2: + IC(0.523 ns) + CELL(0.623 ns) = 1.146 ns; Loc. = LCCOMB_X6_Y13_N26; Fanout = 1; COMB Node = 'Mux~1893'
            Info: 3: + IC(0.363 ns) + CELL(0.206 ns) = 1.715 ns; Loc. = LCCOMB_X6_Y13_N28; Fanout = 1; COMB Node = 'Mux~1894'
            Info: 4: + IC(0.364 ns) + CELL(0.206 ns) = 2.285 ns; Loc. = LCCOMB_X6_Y13_N20; Fanout = 1; COMB Node = 'Mux~1895'
            Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 2.393 ns; Loc. = LCFF_X6_Y13_N21; Fanout = 8; REG Node = 'Q[1]'
            Info: Total cell delay = 1.143 ns ( 47.76 % )
            Info: Total interconnect delay = 1.250 ns ( 52.24 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.747 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X6_Y13_N21; Fanout = 8; REG Node = 'Q[1]'
                Info: Total cell delay = 1.756 ns ( 63.92 % )
                Info: Total interconnect delay = 0.991 ns ( 36.08 % )
            Info: - Longest clock path from clock "clk" to source register is 2.747 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X6_Y13_N5; Fanout = 7; REG Node = 'Q[3]'
                Info: Total cell delay = 1.756 ns ( 63.92 % )
                Info: Total interconnect delay = 0.991 ns ( 36.08 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "Q[0]" (data pin = "din", clock pin = "clk") is 6.009 ns
    Info: + Longest pin to register delay is 8.796 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_4; Fanout = 8; PIN Node = 'din'
        Info: 2: + IC(6.035 ns) + CELL(0.651 ns) = 7.631 ns; Loc. = LCCOMB_X6_Y13_N14; Fanout = 1; COMB Node = 'Mux~1889'
        Info: 3: + IC(0.434 ns) + CELL(0.623 ns) = 8.688 ns; Loc. = LCCOMB_X6_Y13_N16; Fanout = 1; COMB Node = 'Mux~1904'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.796 ns; Loc. = LCFF_X6_Y13_N17; Fanout = 9; REG Node = 'Q[0]'
        Info: Total cell delay = 2.327 ns ( 26.46 % )
        Info: Total interconnect delay = 6.469 ns ( 73.54 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.747 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X6_Y13_N17; Fanout = 9; REG Node = 'Q[0]'
        Info: Total cell delay = 1.756 ns ( 63.92 % )
        Info: Total interconnect delay = 0.991 ns ( 36.08 % )
Info: tco from clock "clk" to destination pin "F" through register "Q[0]" is 9.085 ns
    Info: + Longest clock path from clock "clk" to source register is 2.747 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X6_Y13_N17; Fanout = 9; REG Node = 'Q[0]'
        Info: Total cell delay = 1.756 ns ( 63.92 % )
        Info: Total interconnect delay = 0.991 ns ( 36.08 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.034 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X6_Y13_N17; Fanout = 9; REG Node = 'Q[0]'
        Info: 2: + IC(0.530 ns) + CELL(0.534 ns) = 1.064 ns; Loc. = LCCOMB_X6_Y13_N6; Fanout = 1; COMB Node = 'Mux~1892'
        Info: 3: + IC(0.363 ns) + CELL(0.206 ns) = 1.633 ns; Loc. = LCCOMB_X6_Y13_N0; Fanout = 1; COMB Node = 'LessThan~60'
        Info: 4: + IC(1.175 ns) + CELL(3.226 ns) = 6.034 ns; Loc. = PIN_133; Fanout = 0; PIN Node = 'F'
        Info: Total cell delay = 3.966 ns ( 65.73 % )
        Info: Total interconnect delay = 2.068 ns ( 34.27 % )
Info: th for register "Q[2]" (data pin = "din", clock pin = "clk") is -4.949 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.747 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X6_Y13_N9; Fanout = 9; REG Node = 'Q[2]'
        Info: Total cell delay = 1.756 ns ( 63.92 % )
        Info: Total interconnect delay = 0.991 ns ( 36.08 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 8.002 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_4; Fanout = 8; PIN Node = 'din'
        Info: 2: + IC(6.010 ns) + CELL(0.370 ns) = 7.325 ns; Loc. = LCCOMB_X6_Y13_N10; Fanout = 1; COMB Node = 'Mux~1897'
        Info: 3: + IC(0.363 ns) + CELL(0.206 ns) = 7.894 ns; Loc. = LCCOMB_X6_Y13_N8; Fanout = 1; COMB Node = 'Mux~1898'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.002 ns; Loc. = LCFF_X6_Y13_N9; Fanout = 9; REG Node = 'Q[2]'
        Info: Total cell delay = 1.629 ns ( 20.36 % )
        Info: Total interconnect delay = 6.373 ns ( 79.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Dec 05 15:34:21 2007
    Info: Elapsed time: 00:00:01