📄 schk.tan.rpt
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Timing Analyzer report for schk
Wed Dec 05 15:34:21 2007
Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------+------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.009 ns ; din ; Q[0] ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 9.085 ns ; Q[0] ; F ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -4.949 ns ; din ; Q[2] ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[3] ; Q[1] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C5T144C8 ; ; ; ;
; Timing Models ; Preliminary ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[3] ; Q[1] ; clk ; clk ; None ; None ; 2.393 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[0] ; Q[4] ; clk ; clk ; None ; None ; 2.364 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[2] ; Q[4] ; clk ; clk ; None ; None ; 2.338 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[3] ; Q[0] ; clk ; clk ; None ; None ; 2.308 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[0] ; Q[2] ; clk ; clk ; None ; None ; 2.298 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[2] ; Q[2] ; clk ; clk ; None ; None ; 2.298 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[0] ; Q[3] ; clk ; clk ; None ; None ; 2.274 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[2] ; Q[3] ; clk ; clk ; None ; None ; 2.249 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[1] ; Q[4] ; clk ; clk ; None ; None ; 2.182 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[1] ; Q[2] ; clk ; clk ; None ; None ; 2.150 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[2] ; Q[1] ; clk ; clk ; None ; None ; 2.146 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[1] ; Q[3] ; clk ; clk ; None ; None ; 2.089 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[2] ; Q[0] ; clk ; clk ; None ; None ; 2.065 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[4] ; Q[1] ; clk ; clk ; None ; None ; 1.941 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[4] ; Q[0] ; clk ; clk ; None ; None ; 1.863 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[0] ; Q[1] ; clk ; clk ; None ; None ; 1.551 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[4] ; Q[3] ; clk ; clk ; None ; None ; 1.409 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[1] ; Q[0] ; clk ; clk ; None ; None ; 1.263 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[4] ; Q[2] ; clk ; clk ; None ; None ; 1.231 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[3] ; Q[4] ; clk ; clk ; None ; None ; 1.208 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[3] ; Q[2] ; clk ; clk ; None ; None ; 0.995 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[3] ; Q[3] ; clk ; clk ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[4] ; Q[4] ; clk ; clk ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[0] ; Q[0] ; clk ; clk ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; Q[1] ; Q[1] ; clk ; clk ; None ; None ; 0.501 ns ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+------+----------+
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