schk.tan.qmsg

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register Q\[3\] Q\[1\] 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"Q\[3\]\" and destination register \"Q\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.393 ns + Longest register register " "Info: + Longest register to register delay is 2.393 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[3\] 1 REG LCFF_X6_Y13_N5 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X6_Y13_N5; Fanout = 7; REG Node = 'Q\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "" { Q[3] } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.623 ns) 1.146 ns Mux~1893 2 COMB LCCOMB_X6_Y13_N26 1 " "Info: 2: + IC(0.523 ns) + CELL(0.623 ns) = 1.146 ns; Loc. = LCCOMB_X6_Y13_N26; Fanout = 1; COMB Node = 'Mux~1893'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "1.146 ns" { Q[3] Mux~1893 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 1.715 ns Mux~1894 3 COMB LCCOMB_X6_Y13_N28 1 " "Info: 3: + IC(0.363 ns) + CELL(0.206 ns) = 1.715 ns; Loc. = LCCOMB_X6_Y13_N28; Fanout = 1; COMB Node = 'Mux~1894'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.569 ns" { Mux~1893 Mux~1894 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.206 ns) 2.285 ns Mux~1895 4 COMB LCCOMB_X6_Y13_N20 1 " "Info: 4: + IC(0.364 ns) + CELL(0.206 ns) = 2.285 ns; Loc. = LCCOMB_X6_Y13_N20; Fanout = 1; COMB Node = 'Mux~1895'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.570 ns" { Mux~1894 Mux~1895 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.393 ns Q\[1\] 5 REG LCFF_X6_Y13_N21 8 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 2.393 ns; Loc. = LCFF_X6_Y13_N21; Fanout = 8; REG Node = 'Q\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.108 ns" { Mux~1895 Q[1] } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.143 ns ( 47.76 % ) " "Info: Total cell delay = 1.143 ns ( 47.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.250 ns ( 52.24 % ) " "Info: Total interconnect delay = 1.250 ns ( 52.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.393 ns" { Q[3] Mux~1893 Mux~1894 Mux~1895 Q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.393 ns" { Q[3] Mux~1893 Mux~1894 Mux~1895 Q[1] } { 0.000ns 0.523ns 0.363ns 0.364ns 0.000ns } { 0.000ns 0.623ns 0.206ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.747 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "" { clk } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns clk~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.666 ns) 2.747 ns Q\[1\] 3 REG LCFF_X6_Y13_N21 8 " "Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X6_Y13_N21; Fanout = 8; REG Node = 'Q\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "1.514 ns" { clk~clkctrl Q[1] } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.92 % ) " "Info: Total cell delay = 1.756 ns ( 63.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 36.08 % ) " "Info: Total interconnect delay = 0.991 ns ( 36.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[1] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.747 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "" { clk } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns clk~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.666 ns) 2.747 ns Q\[3\] 3 REG LCFF_X6_Y13_N5 7 " "Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X6_Y13_N5; Fanout = 7; REG Node = 'Q\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "1.514 ns" { clk~clkctrl Q[3] } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.92 % ) " "Info: Total cell delay = 1.756 ns ( 63.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 36.08 % ) " "Info: Total interconnect delay = 0.991 ns ( 36.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[3] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[1] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[3] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.393 ns" { Q[3] Mux~1893 Mux~1894 Mux~1895 Q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.393 ns" { Q[3] Mux~1893 Mux~1894 Mux~1895 Q[1] } { 0.000ns 0.523ns 0.363ns 0.364ns 0.000ns } { 0.000ns 0.623ns 0.206ns 0.206ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[1] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[3] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "" { Q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { Q[1] } {  } {  } } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "Q\[0\] din clk 6.009 ns register " "Info: tsu for register \"Q\[0\]\" (data pin = \"din\", clock pin = \"clk\") is 6.009 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.796 ns + Longest pin register " "Info: + Longest pin to register delay is 8.796 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns din 1 PIN PIN_4 8 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_4; Fanout = 8; PIN Node = 'din'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "" { din } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.035 ns) + CELL(0.651 ns) 7.631 ns Mux~1889 2 COMB LCCOMB_X6_Y13_N14 1 " "Info: 2: + IC(6.035 ns) + CELL(0.651 ns) = 7.631 ns; Loc. = LCCOMB_X6_Y13_N14; Fanout = 1; COMB Node = 'Mux~1889'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "6.686 ns" { din Mux~1889 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.623 ns) 8.688 ns Mux~1904 3 COMB LCCOMB_X6_Y13_N16 1 " "Info: 3: + IC(0.434 ns) + CELL(0.623 ns) = 8.688 ns; Loc. = LCCOMB_X6_Y13_N16; Fanout = 1; COMB Node = 'Mux~1904'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "1.057 ns" { Mux~1889 Mux~1904 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.796 ns Q\[0\] 4 REG LCFF_X6_Y13_N17 9 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.796 ns; Loc. = LCFF_X6_Y13_N17; Fanout = 9; REG Node = 'Q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.108 ns" { Mux~1904 Q[0] } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.327 ns ( 26.46 % ) " "Info: Total cell delay = 2.327 ns ( 26.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.469 ns ( 73.54 % ) " "Info: Total interconnect delay = 6.469 ns ( 73.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "8.796 ns" { din Mux~1889 Mux~1904 Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.796 ns" { din din~combout Mux~1889 Mux~1904 Q[0] } { 0.000ns 0.000ns 6.035ns 0.434ns 0.000ns } { 0.000ns 0.945ns 0.651ns 0.623ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.747 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "" { clk } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns clk~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.666 ns) 2.747 ns Q\[0\] 3 REG LCFF_X6_Y13_N17 9 " "Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X6_Y13_N17; Fanout = 9; REG Node = 'Q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "1.514 ns" { clk~clkctrl Q[0] } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.92 % ) " "Info: Total cell delay = 1.756 ns ( 63.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 36.08 % ) " "Info: Total interconnect delay = 0.991 ns ( 36.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[0] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "8.796 ns" { din Mux~1889 Mux~1904 Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.796 ns" { din din~combout Mux~1889 Mux~1904 Q[0] } { 0.000ns 0.000ns 6.035ns 0.434ns 0.000ns } { 0.000ns 0.945ns 0.651ns 0.623ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[0] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk F Q\[0\] 9.085 ns register " "Info: tco from clock \"clk\" to destination pin \"F\" through register \"Q\[0\]\" is 9.085 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.747 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "" { clk } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns clk~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.666 ns) 2.747 ns Q\[0\] 3 REG LCFF_X6_Y13_N17 9 " "Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X6_Y13_N17; Fanout = 9; REG Node = 'Q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "1.514 ns" { clk~clkctrl Q[0] } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.92 % ) " "Info: Total cell delay = 1.756 ns ( 63.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 36.08 % ) " "Info: Total interconnect delay = 0.991 ns ( 36.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[0] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.034 ns + Longest register pin " "Info: + Longest register to pin delay is 6.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[0\] 1 REG LCFF_X6_Y13_N17 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X6_Y13_N17; Fanout = 9; REG Node = 'Q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "" { Q[0] } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.530 ns) + CELL(0.534 ns) 1.064 ns Mux~1892 2 COMB LCCOMB_X6_Y13_N6 1 " "Info: 2: + IC(0.530 ns) + CELL(0.534 ns) = 1.064 ns; Loc. = LCCOMB_X6_Y13_N6; Fanout = 1; COMB Node = 'Mux~1892'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "1.064 ns" { Q[0] Mux~1892 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 1.633 ns LessThan~60 3 COMB LCCOMB_X6_Y13_N0 1 " "Info: 3: + IC(0.363 ns) + CELL(0.206 ns) = 1.633 ns; Loc. = LCCOMB_X6_Y13_N0; Fanout = 1; COMB Node = 'LessThan~60'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.569 ns" { Mux~1892 LessThan~60 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.175 ns) + CELL(3.226 ns) 6.034 ns F 4 PIN PIN_133 0 " "Info: 4: + IC(1.175 ns) + CELL(3.226 ns) = 6.034 ns; Loc. = PIN_133; Fanout = 0; PIN Node = 'F'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "4.401 ns" { LessThan~60 F } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.966 ns ( 65.73 % ) " "Info: Total cell delay = 3.966 ns ( 65.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.068 ns ( 34.27 % ) " "Info: Total interconnect delay = 2.068 ns ( 34.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "6.034 ns" { Q[0] Mux~1892 LessThan~60 F } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.034 ns" { Q[0] Mux~1892 LessThan~60 F } { 0.000ns 0.530ns 0.363ns 1.175ns } { 0.000ns 0.534ns 0.206ns 3.226ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[0] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "6.034 ns" { Q[0] Mux~1892 LessThan~60 F } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.034 ns" { Q[0] Mux~1892 LessThan~60 F } { 0.000ns 0.530ns 0.363ns 1.175ns } { 0.000ns 0.534ns 0.206ns 3.226ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "Q\[2\] din clk -4.949 ns register " "Info: th for register \"Q\[2\]\" (data pin = \"din\", clock pin = \"clk\") is -4.949 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.747 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "" { clk } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns clk~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.666 ns) 2.747 ns Q\[2\] 3 REG LCFF_X6_Y13_N9 9 " "Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.747 ns; Loc. = LCFF_X6_Y13_N9; Fanout = 9; REG Node = 'Q\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "1.514 ns" { clk~clkctrl Q[2] } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.92 % ) " "Info: Total cell delay = 1.756 ns ( 63.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 36.08 % ) " "Info: Total interconnect delay = 0.991 ns ( 36.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[2] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.002 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.002 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns din 1 PIN PIN_4 8 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_4; Fanout = 8; PIN Node = 'din'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "" { din } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.010 ns) + CELL(0.370 ns) 7.325 ns Mux~1897 2 COMB LCCOMB_X6_Y13_N10 1 " "Info: 2: + IC(6.010 ns) + CELL(0.370 ns) = 7.325 ns; Loc. = LCCOMB_X6_Y13_N10; Fanout = 1; COMB Node = 'Mux~1897'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "6.380 ns" { din Mux~1897 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 7.894 ns Mux~1898 3 COMB LCCOMB_X6_Y13_N8 1 " "Info: 3: + IC(0.363 ns) + CELL(0.206 ns) = 7.894 ns; Loc. = LCCOMB_X6_Y13_N8; Fanout = 1; COMB Node = 'Mux~1898'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.569 ns" { Mux~1897 Mux~1898 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.002 ns Q\[2\] 4 REG LCFF_X6_Y13_N9 9 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.002 ns; Loc. = LCFF_X6_Y13_N9; Fanout = 9; REG Node = 'Q\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "0.108 ns" { Mux~1898 Q[2] } "NODE_NAME" } "" } } { "schk.vhd" "" { Text "D:/xu/序列检测器/schk/schk.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns ( 20.36 % ) " "Info: Total cell delay = 1.629 ns ( 20.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.373 ns ( 79.64 % ) " "Info: Total interconnect delay = 6.373 ns ( 79.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "8.002 ns" { din Mux~1897 Mux~1898 Q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.002 ns" { din din~combout Mux~1897 Mux~1898 Q[2] } { 0.000ns 0.000ns 6.010ns 0.363ns 0.000ns } { 0.000ns 0.945ns 0.370ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "2.747 ns" { clk clk~clkctrl Q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.747 ns" { clk clk~combout clk~clkctrl Q[2] } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "schk" "UNKNOWN" "V1" "D:/xu/序列检测器/schk/db/schk.quartus_db" { Floorplan "D:/xu/序列检测器/schk/" "" "8.002 ns" { din Mux~1897 Mux~1898 Q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.002 ns" { din din~combout Mux~1897 Mux~1898 Q[2] } { 0.000ns 0.000ns 6.010ns 0.363ns 0.000ns } { 0.000ns 0.945ns 0.370ns 0.206ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}