schk.vhd

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

library ieee;
use ieee.std_logic_1164.all;
entity schk is
  port(din,clk,clr: in std_logic;  
                 F: out std_logic   );
end schk;
architecture behave of schk is
      signal Q: integer range 0 to 21;
      signal D: std_logic_vector(20 downto 0);
begin
        D<="101110101101101001011";
process(clk,clr)
begin
 if(clr='1') then Q<=0;
 elsif (clk'event and clk='1')then
      case Q is
          when 0=>  if din=d(20) then Q<=1;   else Q<=0;  end if;
          when 1=>  if din=d(19) then Q<=2;   else Q<=0;  end if;
          when 2=>  if din=d(18) then Q<=3;   else Q<=0;  end if;
          when 3=>  if din=d(17) then Q<=4;   else Q<=0;  end if;
          when 4=>  if din=d(16) then Q<=5;   else Q<=0;  end if;
          when 5=>  if din=d(15) then Q<=6;   else Q<=0;  end if;
          when 6=>  if din=d(14) then Q<=7;   else Q<=0;  end if;
          when 7=>  if din=d(13) then Q<=8;   else Q<=0;  end if;
          when 8=>  if din=d(12) then Q<=9;   else Q<=0;  end if;
          when 9=>  if din=d(11) then Q<=10;  else Q<=0;  end if;
          when 10=> if din=d(10) then Q<=11;  else Q<=0;  end if;
          when 11=> if din=d(9) then Q<=12;   else Q<=0;  end if;
          when 12=> if din=d(8) then Q<=13;   else Q<=0;  end if;
          when 13=> if din=d(7) then Q<=14;   else Q<=0;  end if;
          when 14=> if din=d(6) then Q<=15;   else Q<=0;  end if;
          when 15=> if din=d(5) then Q<=16;   else Q<=0;  end if;
          when 16=> if din=d(4) then Q<=17;   else Q<=0;  end if;
          when 17=> if din=d(3) then Q<=18;   else Q<=0;  end if;
          when 18=> if din=d(2) then Q<=19;   else Q<=0;  end if;
          when 19=> if din=d(1) then Q<=20;   else Q<=0;  end if;
          when 20=> if din=d(0) then Q<=21;   else Q<=0;  end if;
          when others=>Q<=0;
      end case;
  end if;
end process;
process(Q)
  begin
          if Q>0 then F<='1'; else F<='0'; end if;
end process;
end behave;