schk.fit.eqn

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--Q[1] is Q[1] at LCFF_X6_Y13_N21
Q[1] = DFFEAS(A1L13, GLOBAL(A1L2), !GLOBAL(A1L4),  ,  ,  ,  ,  ,  );


--Q[2] is Q[2] at LCFF_X6_Y13_N9
Q[2] = DFFEAS(A1L16, GLOBAL(A1L2), !GLOBAL(A1L4),  ,  ,  ,  ,  ,  );


--Q[4] is Q[4] at LCFF_X6_Y13_N19
Q[4] = DFFEAS(A1L19, GLOBAL(A1L2), !GLOBAL(A1L4),  ,  ,  ,  ,  ,  );


--Q[3] is Q[3] at LCFF_X6_Y13_N5
Q[3] = DFFEAS(A1L21, GLOBAL(A1L2), !GLOBAL(A1L4),  ,  ,  ,  ,  ,  );


--Q[0] is Q[0] at LCFF_X6_Y13_N17
Q[0] = DFFEAS(A1L22, GLOBAL(A1L2), !GLOBAL(A1L4),  ,  ,  ,  ,  ,  );


--A1L10 is Mux~1892 at LCCOMB_X6_Y13_N6
A1L10 = !Q[0] & !Q[4] & !Q[3];


--A1L7 is LessThan~60 at LCCOMB_X6_Y13_N0
A1L7 = Q[2] # Q[1] # !A1L10;


--A1L11 is Mux~1893 at LCCOMB_X6_Y13_N26
A1L11 = Q[2] & (Q[4]) # !Q[2] & Q[3];


--A1L12 is Mux~1894 at LCCOMB_X6_Y13_N28
A1L12 = Q[4] & (A1L11 & (Q[0]) # !A1L11 & !din) # !Q[4] & (din $ (A1L11));


--A1L13 is Mux~1895 at LCCOMB_X6_Y13_N20
A1L13 = Q[0] & !Q[1] & !A1L12 # !Q[0] & Q[1] & A1L12;


--A1L14 is Mux~1896 at LCCOMB_X6_Y13_N12
A1L14 = din & (Q[0] & !Q[2] & Q[1] # !Q[0] & Q[2] & !Q[1]);


--A1L15 is Mux~1897 at LCCOMB_X6_Y13_N10
A1L15 = Q[2] & (Q[0] & !din & !Q[1] # !Q[0] & din & Q[1]);


--A1L16 is Mux~1898 at LCCOMB_X6_Y13_N8
A1L16 = A1L14 & !A1L15 & (!Q[3] # !Q[4]) # !A1L14 & !Q[4] & (A1L15);


--A1L17 is Mux~1899 at LCCOMB_X6_Y13_N22
A1L17 = Q[0] & Q[2] & !din & Q[1];


--A1L18 is Mux~1900 at LCCOMB_X6_Y13_N24
A1L18 = Q[2] & !Q[0] & din & !Q[1] # !Q[2] & (Q[0] $ !din);


--A1L19 is Mux~1901 at LCCOMB_X6_Y13_N18
A1L19 = Q[3] & (!Q[4] & A1L17) # !Q[3] & A1L18 & Q[4];


--A1L20 is Mux~1902 at LCCOMB_X6_Y13_N30
A1L20 = Q[0] & (Q[2] & !din & !Q[1] # !Q[2] & din) # !Q[0] & (din $ (!Q[2] & Q[1]));


--A1L21 is Mux~1903 at LCCOMB_X6_Y13_N4
A1L21 = !Q[4] & (Q[3] & A1L20 # !Q[3] & (A1L17));


--A1L8 is Mux~1888 at LCCOMB_X6_Y13_N2
A1L8 = Q[4] & !Q[3] & (din $ !Q[2]) # !Q[4] & din;


--A1L9 is Mux~1889 at LCCOMB_X6_Y13_N14
A1L9 = din & !Q[4] & (Q[2] # !Q[3]) # !din & !Q[2] & (Q[3] $ Q[4]);


--A1L22 is Mux~1904 at LCCOMB_X6_Y13_N16
A1L22 = !Q[0] & (Q[1] & A1L9 # !Q[1] & (A1L8));


--din is din at PIN_4
--operation mode is input

din = INPUT();


--clk is clk at PIN_17
--operation mode is input

clk = INPUT();


--clr is clr at PIN_18
--operation mode is input

clr = INPUT();


--F is F at PIN_133
--operation mode is output

F = OUTPUT(A1L7);





--A1L4 is clr~clkctrl at CLKCTRL_G1
A1L4 = cycloneii_clkctrl(.INCLK[0] = clr) WITH (clock_type = "Global Clock");


--A1L2 is clk~clkctrl at CLKCTRL_G2
A1L2 = cycloneii_clkctrl(.INCLK[0] = clk) WITH (clock_type = "Global Clock");