produce8.tan.rpt

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

; Slack ; Required tsu ; Actual tsu ; From ; To    ; To Clock ;
+-------+--------------+------------+------+-------+----------+
; N/A   ; None         ; 4.783 ns   ; en   ; iq[2] ; cp       ;
; N/A   ; None         ; 4.783 ns   ; en   ; iq[1] ; cp       ;
; N/A   ; None         ; 4.780 ns   ; en   ; iq[0] ; cp       ;
+-------+--------------+------------+------+-------+----------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+-------+------+------------+
; Slack ; Required tco ; Actual tco ; From  ; To   ; From Clock ;
+-------+--------------+------------+-------+------+------------+
; N/A   ; None         ; 8.057 ns   ; iq[2] ; q[2] ; cp         ;
; N/A   ; None         ; 7.702 ns   ; iq[1] ; q[1] ; cp         ;
; N/A   ; None         ; 7.700 ns   ; iq[0] ; q[0] ; cp         ;
; N/A   ; None         ; 7.368 ns   ; iq[1] ; F    ; cp         ;
+-------+--------------+------------+-------+------+------------+


+-------------------------------------------------------------------+
; th                                                                ;
+---------------+-------------+-----------+------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To    ; To Clock ;
+---------------+-------------+-----------+------+-------+----------+
; N/A           ; None        ; -4.514 ns ; en   ; iq[0] ; cp       ;
; N/A           ; None        ; -4.517 ns ; en   ; iq[2] ; cp       ;
; N/A           ; None        ; -4.517 ns ; en   ; iq[1] ; cp       ;
+---------------+-------------+-----------+------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Dec 06 18:20:53 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off produce8 -c produce8 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "cp" is an undefined clock
Info: Clock "cp" Internal fmax is restricted to 360.1 MHz between source register "iq[0]" and destination register "iq[2]"
    Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.241 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y1_N11; Fanout = 4; REG Node = 'iq[0]'
            Info: 2: + IC(0.482 ns) + CELL(0.651 ns) = 1.133 ns; Loc. = LCCOMB_X4_Y1_N6; Fanout = 1; COMB Node = 'iq[2]~164'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.241 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq[2]'
            Info: Total cell delay = 0.759 ns ( 61.16 % )
            Info: Total interconnect delay = 0.482 ns ( 38.84 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "cp" to destination register is 2.910 ns
                Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 3; CLK Node = 'cp'
                Info: 2: + IC(1.310 ns) + CELL(0.666 ns) = 2.910 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq[2]'
                Info: Total cell delay = 1.600 ns ( 54.98 % )
                Info: Total interconnect delay = 1.310 ns ( 45.02 % )
            Info: - Longest clock path from clock "cp" to source register is 2.910 ns
                Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 3; CLK Node = 'cp'
                Info: 2: + IC(1.310 ns) + CELL(0.666 ns) = 2.910 ns; Loc. = LCFF_X4_Y1_N11; Fanout = 4; REG Node = 'iq[0]'
                Info: Total cell delay = 1.600 ns ( 54.98 % )
                Info: Total interconnect delay = 1.310 ns ( 45.02 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "iq[2]" (data pin = "en", clock pin = "cp") is 4.783 ns
    Info: + Longest pin to register delay is 7.733 ns
        Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_26; Fanout = 3; PIN Node = 'en'
        Info: 2: + IC(6.066 ns) + CELL(0.624 ns) = 7.625 ns; Loc. = LCCOMB_X4_Y1_N6; Fanout = 1; COMB Node = 'iq[2]~164'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.733 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq[2]'
        Info: Total cell delay = 1.667 ns ( 21.56 % )
        Info: Total interconnect delay = 6.066 ns ( 78.44 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "cp" to destination register is 2.910 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 3; CLK Node = 'cp'
        Info: 2: + IC(1.310 ns) + CELL(0.666 ns) = 2.910 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq[2]'
        Info: Total cell delay = 1.600 ns ( 54.98 % )
        Info: Total interconnect delay = 1.310 ns ( 45.02 % )
Info: tco from clock "cp" to destination pin "q[2]" through register "iq[2]" is 8.057 ns
    Info: + Longest clock path from clock "cp" to source register is 2.910 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 3; CLK Node = 'cp'
        Info: 2: + IC(1.310 ns) + CELL(0.666 ns) = 2.910 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq[2]'
        Info: Total cell delay = 1.600 ns ( 54.98 % )
        Info: Total interconnect delay = 1.310 ns ( 45.02 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.843 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq[2]'
        Info: 2: + IC(1.627 ns) + CELL(3.216 ns) = 4.843 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'q[2]'
        Info: Total cell delay = 3.216 ns ( 66.41 % )
        Info: Total interconnect delay = 1.627 ns ( 33.59 % )
Info: th for register "iq[0]" (data pin = "en", clock pin = "cp") is -4.514 ns
    Info: + Longest clock path from clock "cp" to destination register is 2.910 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 3; CLK Node = 'cp'
        Info: 2: + IC(1.310 ns) + CELL(0.666 ns) = 2.910 ns; Loc. = LCFF_X4_Y1_N11; Fanout = 4; REG Node = 'iq[0]'
        Info: Total cell delay = 1.600 ns ( 54.98 % )
        Info: Total interconnect delay = 1.310 ns ( 45.02 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.730 ns
        Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_26; Fanout = 3; PIN Node = 'en'
        Info: 2: + IC(6.064 ns) + CELL(0.623 ns) = 7.622 ns; Loc. = LCCOMB_X4_Y1_N10; Fanout = 1; COMB Node = 'iq[0]~162'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.730 ns; Loc. = LCFF_X4_Y1_N11; Fanout = 4; REG Node = 'iq[0]'
        Info: Total cell delay = 1.666 ns ( 21.55 % )
        Info: Total interconnect delay = 6.064 ns ( 78.45 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Dec 06 18:20:53 2007
    Info: Elapsed time: 00:00:01