📄 produce8.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "cp register register iq\[0\] iq\[2\] 360.1 MHz Internal " "Info: Clock \"cp\" Internal fmax is restricted to 360.1 MHz between source register \"iq\[0\]\" and destination register \"iq\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.241 ns + Longest register register " "Info: + Longest register to register delay is 1.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iq\[0\] 1 REG LCFF_X4_Y1_N11 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y1_N11; Fanout = 4; REG Node = 'iq\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "" { iq[0] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.482 ns) + CELL(0.651 ns) 1.133 ns iq\[2\]~164 2 COMB LCCOMB_X4_Y1_N6 1 " "Info: 2: + IC(0.482 ns) + CELL(0.651 ns) = 1.133 ns; Loc. = LCCOMB_X4_Y1_N6; Fanout = 1; COMB Node = 'iq\[2\]~164'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "1.133 ns" { iq[0] iq[2]~164 } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.241 ns iq\[2\] 3 REG LCFF_X4_Y1_N7 4 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.241 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq\[2\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "0.108 ns" { iq[2]~164 iq[2] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.759 ns ( 61.16 % ) " "Info: Total cell delay = 0.759 ns ( 61.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.482 ns ( 38.84 % ) " "Info: Total interconnect delay = 0.482 ns ( 38.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "1.241 ns" { iq[0] iq[2]~164 iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.241 ns" { iq[0] iq[2]~164 iq[2] } { 0.000ns 0.482ns 0.000ns } { 0.000ns 0.651ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.910 ns + Shortest register " "Info: + Shortest clock path from clock \"cp\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 3 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 3; CLK Node = 'cp'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "" { cp } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.310 ns) + CELL(0.666 ns) 2.910 ns iq\[2\] 2 REG LCFF_X4_Y1_N7 4 " "Info: 2: + IC(1.310 ns) + CELL(0.666 ns) = 2.910 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq\[2\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "1.976 ns" { cp iq[2] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.98 % ) " "Info: Total cell delay = 1.600 ns ( 54.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.310 ns ( 45.02 % ) " "Info: Total interconnect delay = 1.310 ns ( 45.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[2] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 2.910 ns - Longest register " "Info: - Longest clock path from clock \"cp\" to source register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 3 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 3; CLK Node = 'cp'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "" { cp } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.310 ns) + CELL(0.666 ns) 2.910 ns iq\[0\] 2 REG LCFF_X4_Y1_N11 4 " "Info: 2: + IC(1.310 ns) + CELL(0.666 ns) = 2.910 ns; Loc. = LCFF_X4_Y1_N11; Fanout = 4; REG Node = 'iq\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "1.976 ns" { cp iq[0] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.98 % ) " "Info: Total cell delay = 1.600 ns ( 54.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.310 ns ( 45.02 % ) " "Info: Total interconnect delay = 1.310 ns ( 45.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[0] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[2] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[0] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "1.241 ns" { iq[0] iq[2]~164 iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.241 ns" { iq[0] iq[2]~164 iq[2] } { 0.000ns 0.482ns 0.000ns } { 0.000ns 0.651ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[2] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[0] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "" { iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { iq[2] } { } { } } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "iq\[2\] en cp 4.783 ns register " "Info: tsu for register \"iq\[2\]\" (data pin = \"en\", clock pin = \"cp\") is 4.783 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.733 ns + Longest pin register " "Info: + Longest pin to register delay is 7.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns en 1 PIN PIN_26 3 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_26; Fanout = 3; PIN Node = 'en'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "" { en } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.066 ns) + CELL(0.624 ns) 7.625 ns iq\[2\]~164 2 COMB LCCOMB_X4_Y1_N6 1 " "Info: 2: + IC(6.066 ns) + CELL(0.624 ns) = 7.625 ns; Loc. = LCCOMB_X4_Y1_N6; Fanout = 1; COMB Node = 'iq\[2\]~164'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "6.690 ns" { en iq[2]~164 } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.733 ns iq\[2\] 3 REG LCFF_X4_Y1_N7 4 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.733 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq\[2\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "0.108 ns" { iq[2]~164 iq[2] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.667 ns ( 21.56 % ) " "Info: Total cell delay = 1.667 ns ( 21.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.066 ns ( 78.44 % ) " "Info: Total interconnect delay = 6.066 ns ( 78.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "7.733 ns" { en iq[2]~164 iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.733 ns" { en en~combout iq[2]~164 iq[2] } { 0.000ns 0.000ns 6.066ns 0.000ns } { 0.000ns 0.935ns 0.624ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.910 ns - Shortest register " "Info: - Shortest clock path from clock \"cp\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 3 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 3; CLK Node = 'cp'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "" { cp } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.310 ns) + CELL(0.666 ns) 2.910 ns iq\[2\] 2 REG LCFF_X4_Y1_N7 4 " "Info: 2: + IC(1.310 ns) + CELL(0.666 ns) = 2.910 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq\[2\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "1.976 ns" { cp iq[2] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.98 % ) " "Info: Total cell delay = 1.600 ns ( 54.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.310 ns ( 45.02 % ) " "Info: Total interconnect delay = 1.310 ns ( 45.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[2] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "7.733 ns" { en iq[2]~164 iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.733 ns" { en en~combout iq[2]~164 iq[2] } { 0.000ns 0.000ns 6.066ns 0.000ns } { 0.000ns 0.935ns 0.624ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[2] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cp q\[2\] iq\[2\] 8.057 ns register " "Info: tco from clock \"cp\" to destination pin \"q\[2\]\" through register \"iq\[2\]\" is 8.057 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 2.910 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to source register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 3 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 3; CLK Node = 'cp'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "" { cp } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.310 ns) + CELL(0.666 ns) 2.910 ns iq\[2\] 2 REG LCFF_X4_Y1_N7 4 " "Info: 2: + IC(1.310 ns) + CELL(0.666 ns) = 2.910 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq\[2\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "1.976 ns" { cp iq[2] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.98 % ) " "Info: Total cell delay = 1.600 ns ( 54.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.310 ns ( 45.02 % ) " "Info: Total interconnect delay = 1.310 ns ( 45.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[2] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.843 ns + Longest register pin " "Info: + Longest register to pin delay is 4.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iq\[2\] 1 REG LCFF_X4_Y1_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y1_N7; Fanout = 4; REG Node = 'iq\[2\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "" { iq[2] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.627 ns) + CELL(3.216 ns) 4.843 ns q\[2\] 2 PIN PIN_53 0 " "Info: 2: + IC(1.627 ns) + CELL(3.216 ns) = 4.843 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'q\[2\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "4.843 ns" { iq[2] q[2] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.216 ns ( 66.41 % ) " "Info: Total cell delay = 3.216 ns ( 66.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.627 ns ( 33.59 % ) " "Info: Total interconnect delay = 1.627 ns ( 33.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "4.843 ns" { iq[2] q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.843 ns" { iq[2] q[2] } { 0.000ns 1.627ns } { 0.000ns 3.216ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[2] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "4.843 ns" { iq[2] q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.843 ns" { iq[2] q[2] } { 0.000ns 1.627ns } { 0.000ns 3.216ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "iq\[0\] en cp -4.514 ns register " "Info: th for register \"iq\[0\]\" (data pin = \"en\", clock pin = \"cp\") is -4.514 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.910 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 3 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 3; CLK Node = 'cp'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "" { cp } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.310 ns) + CELL(0.666 ns) 2.910 ns iq\[0\] 2 REG LCFF_X4_Y1_N11 4 " "Info: 2: + IC(1.310 ns) + CELL(0.666 ns) = 2.910 ns; Loc. = LCFF_X4_Y1_N11; Fanout = 4; REG Node = 'iq\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "1.976 ns" { cp iq[0] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.98 % ) " "Info: Total cell delay = 1.600 ns ( 54.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.310 ns ( 45.02 % ) " "Info: Total interconnect delay = 1.310 ns ( 45.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[0] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.730 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns en 1 PIN PIN_26 3 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_26; Fanout = 3; PIN Node = 'en'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "" { en } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.064 ns) + CELL(0.623 ns) 7.622 ns iq\[0\]~162 2 COMB LCCOMB_X4_Y1_N10 1 " "Info: 2: + IC(6.064 ns) + CELL(0.623 ns) = 7.622 ns; Loc. = LCCOMB_X4_Y1_N10; Fanout = 1; COMB Node = 'iq\[0\]~162'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "6.687 ns" { en iq[0]~162 } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.730 ns iq\[0\] 3 REG LCFF_X4_Y1_N11 4 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.730 ns; Loc. = LCFF_X4_Y1_N11; Fanout = 4; REG Node = 'iq\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "0.108 ns" { iq[0]~162 iq[0] } "NODE_NAME" } "" } } { "produce8.vhd" "" { Text "D:/xu/序列发生器/produce8/produce8.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.666 ns ( 21.55 % ) " "Info: Total cell delay = 1.666 ns ( 21.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.064 ns ( 78.45 % ) " "Info: Total interconnect delay = 6.064 ns ( 78.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "7.730 ns" { en iq[0]~162 iq[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.730 ns" { en en~combout iq[0]~162 iq[0] } { 0.000ns 0.000ns 6.064ns 0.000ns } { 0.000ns 0.935ns 0.623ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "2.910 ns" { cp iq[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { cp cp~combout iq[0] } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.934ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce8" "UNKNOWN" "V1" "D:/xu/序列发生器/produce8/db/produce8.quartus_db" { Floorplan "D:/xu/序列发生器/produce8/" "" "7.730 ns" { en iq[0]~162 iq[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.730 ns" { en en~combout iq[0]~162 iq[0] } { 0.000ns 0.000ns 6.064ns 0.000ns } { 0.000ns 0.935ns 0.623ns 0.108ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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