produce8.map.rpt

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; -1                 ; -1                 ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                        ;
+----------------------------------+-----------------+-----------------+----------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path           ;
+----------------------------------+-----------------+-----------------+----------------------------------------+
; produce8.vhd                     ; yes             ; User VHDL File  ; D:/xu/序列发生器/produce8/produce8.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total combinational functions               ; 3     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 3     ;
;     -- 3 input functions                    ; 0     ;
;     -- <=2 input functions                  ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 3     ;
;     -- arithmetic mode                      ; 0     ;
; Total registers                             ; 3     ;
; I/O pins                                    ; 7     ;
; Maximum fan-out node                        ; iq[1] ;
; Maximum fan-out                             ; 5     ;
; Total fan-out                               ; 25    ;
; Average fan-out                             ; 1.92  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |produce8                  ; 3 (3)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 7    ; 0            ; |produce8           ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 3     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |produce8|iq[0]            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/xu/序列发生器/produce8/produce8.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Dec 06 18:20:42 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off produce8 -c produce8
Info: Found 2 design units, including 1 entities, in source file produce8.vhd
    Info: Found design unit 1: produce8-rtl
    Info: Found entity 1: produce8
Info: Elaborating entity "produce8" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at produce8.vhd(30): signal "q" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Implemented 10 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 4 output pins
    Info: Implemented 3 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Dec 06 18:20:44 2007
    Info: Elapsed time: 00:00:03