produce8.vhd

来自「序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity produce8 is
  port(cp,clr,en: in std_logic;
                     --d:  in unsigned(3 downto 0);
                     q:  buffer unsigned(2 downto 0);
                     F:  out std_logic);
end produce8;
architecture rtl of produce8 is
       signal iq : unsigned(2 downto 0);
       --signal  a :std_logic_vector(1 downto 0); 
begin
   --a<=a1&a0;
process(cp,en,iq,clr)
  begin
     if(clr='1')then
            iq<=(others=>'0');
     elsif(cp'event and cp='1')then
          
        --if(sh='0')then
            --iq<=d;
        if(en='1' and iq<7)then
           iq<=iq+1;--co<='0';
        elsif(en='1' and iq=7)then
           iq<=('1','1','1');--co<='1';
        end if;
      end if;
   q<=iq;
   F<=q(1);
end process;
end rtl;