produce8.map.eqn

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--iq[0] is iq[0]
iq[0] = DFFEAS(A1L7, cp, !clr,  ,  ,  ,  ,  ,  );


--iq[1] is iq[1]
iq[1] = DFFEAS(A1L9, cp, !clr,  ,  ,  ,  ,  ,  );


--iq[2] is iq[2]
iq[2] = DFFEAS(A1L11, cp, !clr,  ,  ,  ,  ,  ,  );


--A1L7 is iq[0]~162
A1L7 = iq[0] & (iq[1] & iq[2] # !en) # !iq[0] & (en);


--A1L9 is iq[1]~163
A1L9 = iq[1] & (iq[2] # !en # !iq[0]) # !iq[1] & (iq[0] & en);


--A1L11 is iq[2]~164
A1L11 = iq[2] # iq[0] & iq[1] & en;


--en is en
--operation mode is input

en = INPUT();


--cp is cp
--operation mode is input

cp = INPUT();


--clr is clr
--operation mode is input

clr = INPUT();


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(iq[0]);


--q[1] is q[1]
--operation mode is output

q[1] = OUTPUT(iq[1]);


--q[2] is q[2]
--operation mode is output

q[2] = OUTPUT(iq[2]);


--F is F
--operation mode is output

F = OUTPUT(iq[1]);