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📄 produce.map.eqn

📁 序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器
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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L12Q is F~reg0
A1L12Q = DFFEAS(A1L13, clock,  ,  ,  ,  ,  ,  ,  );


--count[2] is count[2]
count[2] = DFFEAS(A1L10, clk, !clr,  ,  ,  ,  ,  ,  );


--count[1] is count[1]
count[1] = DFFEAS(A1L8, clk, !clr,  ,  ,  ,  ,  ,  );


--count[0] is count[0]
count[0] = DFFEAS(A1L6, clk, !clr,  ,  ,  ,  ,  ,  );


--A1L13 is Z~50
A1L13 = count[2] & (!count[0] # !count[1]) # !count[2] & (count[1] # count[0]);


--A1L10 is count[2]~43
A1L10 = count[2] $ (count[1] & count[0]);


--A1L8 is count[1]~44
A1L8 = count[1] $ count[0];


--A1L6 is count[0]~45
A1L6 = !count[0];


--clock is clock
--operation mode is input

clock = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--clr is clr
--operation mode is input

clr = INPUT();


--F is F
--operation mode is output

F = OUTPUT(A1L12Q);


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