produce.tan.qmsg

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register count\[1\] count\[2\] 360.1 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 360.1 MHz between source register \"count\[1\]\" and destination register \"count\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.174 ns + Longest register register " "Info: + Longest register to register delay is 1.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LCFF_X1_Y5_N19 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N19; Fanout = 3; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "" { count[1] } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.624 ns) 1.066 ns count\[2\]~43 2 COMB LCCOMB_X1_Y5_N6 1 " "Info: 2: + IC(0.442 ns) + CELL(0.624 ns) = 1.066 ns; Loc. = LCCOMB_X1_Y5_N6; Fanout = 1; COMB Node = 'count\[2\]~43'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "1.066 ns" { count[1] count[2]~43 } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.174 ns count\[2\] 3 REG LCFF_X1_Y5_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.174 ns; Loc. = LCFF_X1_Y5_N7; Fanout = 2; REG Node = 'count\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "0.108 ns" { count[2]~43 count[2] } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.732 ns ( 62.35 % ) " "Info: Total cell delay = 0.732 ns ( 62.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.442 ns ( 37.65 % ) " "Info: Total interconnect delay = 0.442 ns ( 37.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "1.174 ns" { count[1] count[2]~43 count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.174 ns" { count[1] count[2]~43 count[2] } { 0.000ns 0.442ns 0.000ns } { 0.000ns 0.624ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.440 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns clk 1 CLK PIN_25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_25; Fanout = 3; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "" { clk } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.440 ns count\[2\] 2 REG LCFF_X1_Y5_N7 2 " "Info: 2: + IC(0.839 ns) + CELL(0.666 ns) = 2.440 ns; Loc. = LCFF_X1_Y5_N7; Fanout = 2; REG Node = 'count\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "1.505 ns" { clk count[2] } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 65.61 % ) " "Info: Total cell delay = 1.601 ns ( 65.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.839 ns ( 34.39 % ) " "Info: Total interconnect delay = 0.839 ns ( 34.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "2.440 ns" { clk count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~combout count[2] } { 0.000ns 0.000ns 0.839ns } { 0.000ns 0.935ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.440 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns clk 1 CLK PIN_25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_25; Fanout = 3; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "" { clk } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.440 ns count\[1\] 2 REG LCFF_X1_Y5_N19 3 " "Info: 2: + IC(0.839 ns) + CELL(0.666 ns) = 2.440 ns; Loc. = LCFF_X1_Y5_N19; Fanout = 3; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "1.505 ns" { clk count[1] } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 65.61 % ) " "Info: Total cell delay = 1.601 ns ( 65.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.839 ns ( 34.39 % ) " "Info: Total interconnect delay = 0.839 ns ( 34.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "2.440 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~combout count[1] } { 0.000ns 0.000ns 0.839ns } { 0.000ns 0.935ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "2.440 ns" { clk count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~combout count[2] } { 0.000ns 0.000ns 0.839ns } { 0.000ns 0.935ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "2.440 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~combout count[1] } { 0.000ns 0.000ns 0.839ns } { 0.000ns 0.935ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "1.174 ns" { count[1] count[2]~43 count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.174 ns" { count[1] count[2]~43 count[2] } { 0.000ns 0.442ns 0.000ns } { 0.000ns 0.624ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "2.440 ns" { clk count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~combout count[2] } { 0.000ns 0.000ns 0.839ns } { 0.000ns 0.935ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "2.440 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~combout count[1] } { 0.000ns 0.000ns 0.839ns } { 0.000ns 0.935ns 0.666ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "" { count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { count[2] } {  } {  } } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 20 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock F F~reg0 8.577 ns register " "Info: tco from clock \"clock\" to destination pin \"F\" through register \"F~reg0\" is 8.577 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.370 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.370 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns clock 1 CLK PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "" { clock } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.770 ns) + CELL(0.666 ns) 3.370 ns F~reg0 2 REG LCFF_X1_Y5_N17 1 " "Info: 2: + IC(1.770 ns) + CELL(0.666 ns) = 3.370 ns; Loc. = LCFF_X1_Y5_N17; Fanout = 1; REG Node = 'F~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "2.436 ns" { clock F~reg0 } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 47.48 % ) " "Info: Total cell delay = 1.600 ns ( 47.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.770 ns ( 52.52 % ) " "Info: Total interconnect delay = 1.770 ns ( 52.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "3.370 ns" { clock F~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.370 ns" { clock clock~combout F~reg0 } { 0.000ns 0.000ns 1.770ns } { 0.000ns 0.934ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 44 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.903 ns + Longest register pin " "Info: + Longest register to pin delay is 4.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns F~reg0 1 REG LCFF_X1_Y5_N17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N17; Fanout = 1; REG Node = 'F~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "" { F~reg0 } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.677 ns) + CELL(3.226 ns) 4.903 ns F 2 PIN PIN_48 0 " "Info: 2: + IC(1.677 ns) + CELL(3.226 ns) = 4.903 ns; Loc. = PIN_48; Fanout = 0; PIN Node = 'F'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "4.903 ns" { F~reg0 F } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "D:/xu/序列发生器/produce/produce.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.226 ns ( 65.80 % ) " "Info: Total cell delay = 3.226 ns ( 65.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.677 ns ( 34.20 % ) " "Info: Total interconnect delay = 1.677 ns ( 34.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "4.903 ns" { F~reg0 F } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.903 ns" { F~reg0 F } { 0.000ns 1.677ns } { 0.000ns 3.226ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "3.370 ns" { clock F~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.370 ns" { clock clock~combout F~reg0 } { 0.000ns 0.000ns 1.770ns } { 0.000ns 0.934ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "D:/xu/序列发生器/produce/db/produce.quartus_db" { Floorplan "D:/xu/序列发生器/produce/" "" "4.903 ns" { F~reg0 F } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.903 ns" { F~reg0 F } { 0.000ns 1.677ns } { 0.000ns 3.226ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 06 18:25:37 2007 " "Info: Processing ended: Thu Dec 06 18:25:37 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}