produce.vhd

序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity produce is
  port(clk,clr,clock: in std_logic;
                     --d:  in unsigned(3 downto 0);
                     --q:  buffer unsigned(2 downto 0);
                     F:  out std_logic);
end produce;
architecture rtl of produce is
       signal count: std_logic_vector(2 downto 0);
       --signal  a :std_logic_vector(1 downto 0);
       signal Z:     std_logic:='0';
begin
     process(clk,clr)
        begin
       if(clr='1')then count<="000";
       else
         if(clk'event and clk='1')then
              if(count="111")then count<="000";
              else  count<=count+'1';
              end if;
         end if;
       end if;
     end process;
process(count)
begin
    case count is
       when "000"=>Z<='0'; 
       when "001"=>Z<='1'; 
       when "010"=>Z<='1'; 
       when "011"=>Z<='1'; 
       when "100"=>Z<='1'; 
       when "101"=>Z<='1'; 
       when "110"=>Z<='1'; 
       when "111"=>Z<='0'; 
       when others=>Z<='0'; 
   end case;
--F<=Z;
end process;
process(clock,Z)
     begin
     if(clock'event and clock='1')then
        F<=Z;
     end if;
end process;
end rtl;