📄 produce.fit.rpt
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; clock ; 1 ;
; count[0]~45 ; 1 ;
; count[1]~44 ; 1 ;
; count[2]~43 ; 1 ;
; Z~50 ; 1 ;
; F~reg0 ; 1 ;
+-------------+-------------------+
+---------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; Block interconnects ; 4 / 15,666 ( < 1 % ) ;
; C16 interconnects ; 1 / 812 ( < 1 % ) ;
; C4 interconnects ; 1 / 11,424 ( < 1 % ) ;
; Direct links ; 0 / 15,666 ( 0 % ) ;
; Global clocks ; 0 / 8 ( 0 % ) ;
; Local interconnects ; 3 / 4,608 ( < 1 % ) ;
; R24 interconnects ; 0 / 652 ( 0 % ) ;
; R4 interconnects ; 3 / 13,328 ( < 1 % ) ;
+----------------------------+----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 4.00) ; Number of LABs (Total = 1) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 1) ;
+------------------------------------+-----------------------------+
; 1 Async. clear ; 1 ;
; 2 Clocks ; 1 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
Info: Processing started: Thu Dec 06 18:25:29 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off produce -c produce
Info: Selected device EP2C5T144C8 for design "produce"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP2C5T144I8 is compatible
Info: Device EP2C8T144C8 is compatible
Info: Device EP2C8T144I8 is compatible
Info: Starting register packing
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 0.989 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y5; Fanout = 3; REG Node = 'count[1]'
Info: 2: + IC(0.511 ns) + CELL(0.370 ns) = 0.881 ns; Loc. = LAB_X1_Y5; Fanout = 1; COMB Node = 'count[2]~43'
Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.989 ns; Loc. = LAB_X1_Y5; Fanout = 2; REG Node = 'count[2]'
Info: Total cell delay = 0.478 ns ( 48.33 % )
Info: Total interconnect delay = 0.511 ns ( 51.67 % )
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Timing characteristics of device EP2C5T144C8 are preliminary
Warning: Found 1 output pins without output pin load capacitance assignment
Warning: Pin "F" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
Info: Processing ended: Thu Dec 06 18:25:32 2007
Info: Elapsed time: 00:00:03
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