📄 vgainterface.tan.qmsg
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{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] vga_read clock0 2.715 ns " "Info: Found hold time violation between source pin or register tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] and destination pin or register vga_read for clock clock0 (Hold time is 2.715 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.773 ns + Largest " "Info: + Largest clock skew is 3.773 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 destination 12.397 ns + Longest register " "Info: + Longest clock path from clock clock0 to destination register is 12.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.942 ns) + CELL(0.720 ns) 8.797 ns clock_25mhz 2 REG LC_X11_Y9_N2 44 " "Info: 2: + IC(6.942 ns) + CELL(0.720 ns) = 8.797 ns; Loc. = LC_X11_Y9_N2; Fanout = 44; REG Node = 'clock_25mhz'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.662 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 67 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.053 ns) + CELL(0.547 ns) 12.397 ns vga_read 3 REG LC_X12_Y10_N4 1 " "Info: 3: + IC(3.053 ns) + CELL(0.547 ns) = 12.397 ns; Loc. = LC_X12_Y10_N4; Fanout = 1; REG Node = 'vga_read'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.600 ns" { clock_25mhz vga_read } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 168 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 19.38 % " "Info: Total cell delay = 2.402 ns ( 19.38 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.995 ns 80.62 % " "Info: Total interconnect delay = 9.995 ns ( 80.62 % )" { } { } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.397 ns" { clock0 clock_25mhz vga_read } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 8.624 ns - Shortest register " "Info: - Shortest clock path from clock clock0 to source register is 8.624 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.942 ns) + CELL(0.547 ns) 8.624 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] 2 REG LC_X12_Y10_N2 2 " "Info: 2: + IC(6.942 ns) + CELL(0.547 ns) = 8.624 ns; Loc. = LC_X12_Y10_N2; Fanout = 2; REG Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\]'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.489 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/VGA_test1/vgainterface/db/altsyncram_qcr.tdf" 40 15 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.682 ns 19.50 % " "Info: Total cell delay = 1.682 ns ( 19.50 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.942 ns 80.50 % " "Info: Total interconnect delay = 6.942 ns ( 80.50 % )" { } { } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.624 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.397 ns" { clock0 clock_25mhz vga_read } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.624 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns - " "Info: - Micro clock to output delay of source is 0.173 ns" { } { { "F:/program_test/VGA_test1/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/VGA_test1/vgainterface/db/altsyncram_qcr.tdf" 40 15 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.897 ns - Shortest register register " "Info: - Shortest register to register delay is 0.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] 1 REG LC_X12_Y10_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N2; Fanout = 2; REG Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\]'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/VGA_test1/vgainterface/db/altsyncram_qcr.tdf" 40 15 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|mux_rab:mux2\|w_result37w~38 2 COMB LC_X12_Y10_N2 2 " "Info: 2: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC_X12_Y10_N2; Fanout = 2; COMB Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|mux_rab:mux2\|w_result37w~38'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.291 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/mux_rab.tdf" "" "" { Text "F:/program_test/vgainterface/db/mux_rab.tdf" 39 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 0.519 ns vga_read~96 3 COMB LC_X12_Y10_N3 2 " "Info: 3: + IC(0.140 ns) + CELL(0.088 ns) = 0.519 ns; Loc. = LC_X12_Y10_N3; Fanout = 2; COMB Node = 'vga_read~96'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.228 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 vga_read~96 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 168 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.238 ns) 0.897 ns vga_read 4 REG LC_X12_Y10_N4 1 " "Info: 4: + IC(0.140 ns) + CELL(0.238 ns) = 0.897 ns; Loc. = LC_X12_Y10_N4; Fanout = 1; REG Node = 'vga_read'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.378 ns" { vga_read~96 vga_read } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 168 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.617 ns 68.78 % " "Info: Total cell delay = 0.617 ns ( 68.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.280 ns 31.22 % " "Info: Total interconnect delay = 0.280 ns ( 31.22 % )" { } { } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.897 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 vga_read~96 vga_read } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" { } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 168 -1 0 } } } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.397 ns" { clock0 clock_25mhz vga_read } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.624 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.897 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 vga_read~96 vga_read } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock0 vga_vs_control vga_vs_control~reg0 15.717 ns register " "Info: tco from clock clock0 to destination pin vga_vs_control through register vga_vs_control~reg0 is 15.717 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 12.397 ns + Longest register " "Info: + Longest clock path from clock clock0 to source register is 12.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.942 ns) + CELL(0.720 ns) 8.797 ns clock_25mhz 2 REG LC_X11_Y9_N2 44 " "Info: 2: + IC(6.942 ns) + CELL(0.720 ns) = 8.797 ns; Loc. = LC_X11_Y9_N2; Fanout = 44; REG Node = 'clock_25mhz'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.662 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 67 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.053 ns) + CELL(0.547 ns) 12.397 ns vga_vs_control~reg0 3 REG LC_X11_Y12_N2 1 " "Info: 3: + IC(3.053 ns) + CELL(0.547 ns) = 12.397 ns; Loc. = LC_X11_Y12_N2; Fanout = 1; REG Node = 'vga_vs_control~reg0'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.600 ns" { clock_25mhz vga_vs_control~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 130 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 19.38 % " "Info: Total cell delay = 2.402 ns ( 19.38 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.995 ns 80.62 % " "Info: Total interconnect delay = 9.995 ns ( 80.62 % )" { } { } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.397 ns" { clock0 clock_25mhz vga_vs_control~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 130 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.147 ns + Longest register pin " "Info: + Longest register to pin delay is 3.147 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vs_control~reg0 1 REG LC_X11_Y12_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N2; Fanout = 1; REG Node = 'vga_vs_control~reg0'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { vga_vs_control~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 130 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.525 ns) + CELL(1.622 ns) 3.147 ns vga_vs_control 2 PIN PIN_140 0 " "Info: 2: + IC(1.525 ns) + CELL(1.622 ns) = 3.147 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'vga_vs_control'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.147 ns" { vga_vs_control~reg0 vga_vs_control } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 51.54 % " "Info: Total cell delay = 1.622 ns ( 51.54 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.525 ns 48.46 % " "Info: Total interconnect delay = 1.525 ns ( 48.46 % )" { } { } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.147 ns" { vga_vs_control~reg0 vga_vs_control } "NODE_NAME" } } } } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.397 ns" { clock0 clock_25mhz vga_vs_control~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.147 ns" { vga_vs_control~reg0 vga_vs_control } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clock0 vga_read_dispaly vga_read_dispaly~reg0 15.461 ns register " "Info: Minimum tco from clock clock0 to destination pin vga_read_dispaly through register vga_read_dispaly~reg0 is 15.461 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 12.397 ns + Shortest register " "Info: + Shortest clock path from clock clock0 to source register is 12.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.942 ns) + CELL(0.720 ns) 8.797 ns clock_25mhz 2 REG LC_X11_Y9_N2 44 " "Info: 2: + IC(6.942 ns) + CELL(0.720 ns) = 8.797 ns; Loc. = LC_X11_Y9_N2; Fanout = 44; REG Node = 'clock_25mhz'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.662 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 67 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.053 ns) + CELL(0.547 ns) 12.397 ns vga_read_dispaly~reg0 3 REG LC_X11_Y12_N7 1 " "Info: 3: + IC(3.053 ns) + CELL(0.547 ns) = 12.397 ns; Loc. = LC_X11_Y12_N7; Fanout = 1; REG Node = 'vga_read_dispaly~reg0'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.600 ns" { clock_25mhz vga_read_dispaly~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 141 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 19.38 % " "Info: Total cell delay = 2.402 ns ( 19.38 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.995 ns 80.62 % " "Info: Total interconnect delay = 9.995 ns ( 80.62 % )" { } { } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.397 ns" { clock0 clock_25mhz vga_read_dispaly~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 141 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.891 ns + Shortest register pin " "Info: + Shortest register to pin delay is 2.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_read_dispaly~reg0 1 REG LC_X11_Y12_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N7; Fanout = 1; REG Node = 'vga_read_dispaly~reg0'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { vga_read_dispaly~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 141 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.269 ns) + CELL(1.622 ns) 2.891 ns vga_read_dispaly 2 PIN PIN_131 0 " "Info: 2: + IC(1.269 ns) + CELL(1.622 ns) = 2.891 ns; Loc. = PIN_131; Fanout = 0; PIN Node = 'vga_read_dispaly'" { } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.891 ns" { vga_read_dispaly~reg0 vga_read_dispaly } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test1/vgainterface/vgainterface.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 56.11 % " "Info: Total cell delay = 1.622 ns ( 56.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.269 ns 43.89 % " "Info: Total interconnect delay = 1.269 ns ( 43.89 % )" { } { } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.891 ns" { vga_read_dispaly~reg0 vga_read_dispaly } "NODE_NAME" } } } } 0} } { { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.397 ns" { clock0 clock_25mhz vga_read_dispaly~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test1/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test1/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.891 ns" { vga_read_dispaly~reg0 vga_read_dispaly } "NODE_NAME" } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 26 12:19:52 2005 " "Info: Processing ended: Tue Apr 26 12:19:52 2005" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0} } { } 0}
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