display.vhd

FPGA控制串行AD（AD0804）,状态机实现

--串行七段数码管驱动程序
------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity display is
port
(clock:in std_logic;
 numA,numB,numC,numD:in std_logic_vector(3 downto 0);
 en:out std_logic_vector(0 to 3);--分别接4个数码管的公共端
 display:out std_logic_vector(0 to 6)---接数码管的7个控制端
);
end;

architecture decoder of display is
signal counter:integer range 0 to 3;
begin
	process(clock)
	variable num:std_logic_vector(3 downto 0);
	begin
	 if rising_edge(clock) then
	   if counter=3 then
		counter<=0;
	   else
		counter<=counter+1;
	   end if;
	   case counter is
		when 0=>
		     en<="1000";--点亮第一个数码管，屏蔽其他5个数码管
		     num:=numA;--显示第一个数
		when 1=>
		     en<="0100";--点亮第二个数码管
		     num:=numB;--显示第二个数
		when 2=>
		     en<="0010";
		     num:=numC;
		when 3=>
		     en<="0001";
		     num:=numD;
--		when 4=>
--		     en<="111101";
--		     num:=numE;
--		when 5=>
--		     en<="111110";
--		     num:=numF;
		when others=>
		     en<="0000";	
		     num:="0000";
		end case;
		case num is
			when "0000"=>display<="1111110";
			when "0001"=>display<="0110000";
			when "0010"=>display<="1101101";
			when "0011"=>display<="1111001";
			when "0100"=>display<="0110011";
			when "0101"=>display<="1011011";
			when "0110"=>display<="1011111";
			when "0111"=>display<="1110000";
			when "1000"=>display<="1111111";
			when "1001"=>display<="1110011";
			when "1010"=>display<="1110111";
			when "1011"=>display<="0011111";
			when "1100"=>display<="1001110";
			when "1101"=>display<="0111101";
			when "1110"=>display<="1001111";
			when "1111"=>display<="1000111";
			when others=>display<="0000000";
		end case;
	     end if;
	end process;
end;