ad.tan.qmsg

FPGA控制串行AD（AD0804）,状态机实现

{ "Info" "ITDB_TSU_RESULT" "ad0804:u2\|current_state.convert ad_int clk 6.100 ns register " "Info: tsu for register \"ad0804:u2\|current_state.convert\" (data pin = \"ad_int\", clock pin = \"clk\") is 6.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest pin register " "Info: + Longest pin to register delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns ad_int 1 PIN PIN_62 2 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_62; Fanout = 2; PIN Node = 'ad_int'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ad_int } "NODE_NAME" } } { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.200 ns) 8.600 ns ad0804:u2\|current_state.convert 2 REG LC4_F41 2 " "Info: 2: + IC(4.300 ns) + CELL(1.200 ns) = 8.600 ns; Loc. = LC4_F41; Fanout = 2; REG Node = 'ad0804:u2\|current_state.convert'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.500 ns" { ad_int ad0804:u2|current_state.convert } "NODE_NAME" } } { "ad0804.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad0804.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.300 ns ( 50.00 % ) " "Info: Total cell delay = 4.300 ns ( 50.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 50.00 % ) " "Info: Total interconnect delay = 4.300 ns ( 50.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.600 ns" { ad_int ad0804:u2|current_state.convert } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.600 ns" { ad_int ad_int~out ad0804:u2|current_state.convert } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.100ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "ad0804.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad0804.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 21; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk1k:u1\|clk2 2 REG LC3_F41 13 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC3_F41; Fanout = 13; REG Node = 'clk1k:u1\|clk2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1k:u1|clk2 } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 3.200 ns ad0804:u2\|current_state.convert 3 REG LC4_F41 2 " "Info: 3: + IC(0.200 ns) + CELL(0.000 ns) = 3.200 ns; Loc. = LC4_F41; Fanout = 2; REG Node = 'ad0804:u2\|current_state.convert'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { clk1k:u1|clk2 ad0804:u2|current_state.convert } "NODE_NAME" } } { "ad0804.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad0804.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 50.00 % ) " "Info: Total cell delay = 1.600 ns ( 50.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 50.00 % ) " "Info: Total interconnect delay = 1.600 ns ( 50.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { clk clk1k:u1|clk2 ad0804:u2|current_state.convert } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.200 ns" { clk clk~out clk1k:u1|clk2 ad0804:u2|current_state.convert } { 0.000ns 0.000ns 1.400ns 0.200ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.600 ns" { ad_int ad0804:u2|current_state.convert } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.600 ns" { ad_int ad_int~out ad0804:u2|current_state.convert } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.100ns 1.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { clk clk1k:u1|clk2 ad0804:u2|current_state.convert } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.200 ns" { clk clk~out clk1k:u1|clk2 ad0804:u2|current_state.convert } { 0.000ns 0.000ns 1.400ns 0.200ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk displayA\[0\] display:u4\|display\[0\] 20.900 ns register " "Info: tco from clock \"clk\" to destination pin \"displayA\[0\]\" through register \"display:u4\|display\[0\]\" is 20.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.800 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 21; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk1k:u1\|clk1 2 REG LC1_J4 14 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_J4; Fanout = 14; REG Node = 'clk1k:u1\|clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1k:u1|clk1 } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.800 ns) + CELL(0.000 ns) 7.800 ns display:u4\|display\[0\] 3 REG LC6_F43 1 " "Info: 3: + IC(4.800 ns) + CELL(0.000 ns) = 7.800 ns; Loc. = LC6_F43; Fanout = 1; REG Node = 'display:u4\|display\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.800 ns" { clk1k:u1|clk1 display:u4|display[0] } "NODE_NAME" } } { "display.vhd" "" { Text "F:/QuartusII work/AD0804/AD/display.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 20.51 % ) " "Info: Total cell delay = 1.600 ns ( 20.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.200 ns ( 79.49 % ) " "Info: Total interconnect delay = 6.200 ns ( 79.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.800 ns" { clk clk1k:u1|clk1 display:u4|display[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.800 ns" { clk clk~out clk1k:u1|clk1 display:u4|display[0] } { 0.000ns 0.000ns 1.400ns 4.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "display.vhd" "" { Text "F:/QuartusII work/AD0804/AD/display.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.000 ns + Longest register pin " "Info: + Longest register to pin delay is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns display:u4\|display\[0\] 1 REG LC6_F43 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_F43; Fanout = 1; REG Node = 'display:u4\|display\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { display:u4|display[0] } "NODE_NAME" } } { "display.vhd" "" { Text "F:/QuartusII work/AD0804/AD/display.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(8.600 ns) 12.000 ns displayA\[0\] 2 PIN PIN_148 0 " "Info: 2: + IC(3.400 ns) + CELL(8.600 ns) = 12.000 ns; Loc. = PIN_148; Fanout = 0; PIN Node = 'displayA\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.000 ns" { display:u4|display[0] displayA[0] } "NODE_NAME" } } { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns ( 71.67 % ) " "Info: Total cell delay = 8.600 ns ( 71.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns ( 28.33 % ) " "Info: Total interconnect delay = 3.400 ns ( 28.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.000 ns" { display:u4|display[0] displayA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.000 ns" { display:u4|display[0] displayA[0] } { 0.000ns 3.400ns } { 0.000ns 8.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.800 ns" { clk clk1k:u1|clk1 display:u4|display[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.800 ns" { clk clk~out clk1k:u1|clk1 display:u4|display[0] } { 0.000ns 0.000ns 1.400ns 4.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.000 ns" { display:u4|display[0] displayA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.000 ns" { display:u4|display[0] displayA[0] } { 0.000ns 3.400ns } { 0.000ns 8.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ad0804:u2\|data_r\[3\] data_i\[3\] clk -2.800 ns register " "Info: th for register \"ad0804:u2\|data_r\[3\]\" (data pin = \"data_i\[3\]\", clock pin = \"clk\") is -2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.700 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 21; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk1k:u1\|clk2 2 REG LC3_F41 13 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC3_F41; Fanout = 13; REG Node = 'clk1k:u1\|clk2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1k:u1|clk2 } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.000 ns) 4.700 ns ad0804:u2\|data_r\[3\] 3 REG LC6_F39 1 " "Info: 3: + IC(1.700 ns) + CELL(0.000 ns) = 4.700 ns; Loc. = LC6_F39; Fanout = 1; REG Node = 'ad0804:u2\|data_r\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { clk1k:u1|clk2 ad0804:u2|data_r[3] } "NODE_NAME" } } { "ad0804.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad0804.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 34.04 % ) " "Info: Total cell delay = 1.600 ns ( 34.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 65.96 % ) " "Info: Total interconnect delay = 3.100 ns ( 65.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.700 ns" { clk clk1k:u1|clk2 ad0804:u2|data_r[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.700 ns" { clk clk~out clk1k:u1|clk2 ad0804:u2|data_r[3] } { 0.000ns 0.000ns 1.400ns 1.700ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "ad0804.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad0804.vhd" 98 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns data_i\[3\] 1 PIN PIN_67 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_67; Fanout = 1; PIN Node = 'data_i\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_i[3] } "NODE_NAME" } } { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.000 ns) 8.400 ns ad0804:u2\|data_r\[3\] 2 REG LC6_F39 1 " "Info: 2: + IC(4.300 ns) + CELL(1.000 ns) = 8.400 ns; Loc. = LC6_F39; Fanout = 1; REG Node = 'ad0804:u2\|data_r\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { data_i[3] ad0804:u2|data_r[3] } "NODE_NAME" } } { "ad0804.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad0804.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.100 ns ( 48.81 % ) " "Info: Total cell delay = 4.100 ns ( 48.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 51.19 % ) " "Info: Total interconnect delay = 4.300 ns ( 51.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.400 ns" { data_i[3] ad0804:u2|data_r[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.400 ns" { data_i[3] data_i[3]~out ad0804:u2|data_r[3] } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.100ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.700 ns" { clk clk1k:u1|clk2 ad0804:u2|data_r[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.700 ns" { clk clk~out clk1k:u1|clk2 ad0804:u2|data_r[3] } { 0.000ns 0.000ns 1.400ns 1.700ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.400 ns" { data_i[3] ad0804:u2|data_r[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.400 ns" { data_i[3] data_i[3]~out ad0804:u2|data_r[3] } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.100ns 1.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 07 15:19:14 2007 " "Info: Processing ended: Wed Nov 07 15:19:14 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}