clk1k.vhd

来自「FPGA控制串行AD（AD0804）,状态机实现」· VHDL 代码 · 共 45 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk1k is
port 
(clkin:in std_logic;
 newclk1:out std_logic;
 newclk2:out std_logic
);
end;

architecture behave of clk1k is
signal counter1:integer range 0 to 12499;
signal counter2:integer range 0 to 19;

signal clk1,clk2:std_logic;
begin
	process(clkin)
	begin
		if rising_edge(clkin) then
		   if counter1=12499 then
			counter1<=0;
            clk1<=not clk1;
		   else counter1<=counter1+1;
		   end if;
		end if;
	end process;
   newclk1<=clk1;


	process(clkin)
	begin
		if rising_edge(clkin) then
		   if counter2=19 then
			counter2<=0;
            clk2<=not clk2;
		   else counter2<=counter2+1;
		   end if;
		end if;
	end process;
   newclk2<=clk2;

end;