fenwei.vhd

来自「FPGA控制串行AD（AD0804）,状态机实现」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;


entity fenwei is
port
(numin:in std_logic_vector(7 downto 0);
 numA,numB:out std_logic_vector(3 downto 0)
);
end;

architecture behave of fenwei is
begin
	process(numin)
	begin
		numA<=numin(3 downto 0);
		numB<=numin(7 downto 4);
	end process;
end;