project1.map.summary

FPGA DS18B20 测试温度 VHDL源码

Analysis & Synthesis Status : Successful - Thu Sep 20 15:32:36 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : project1
Top-level Entity Name : Project1
Family : ACEX1K
Total logic elements : 191
Total pins : 15
Total memory bits : 0
Total PLLs : 0