system5501.h

TMS320VC5502 DSP BootLoad源码 包括CPLD源码

#ifndef _SYSTEM5501_H
#define _SYSTEM5501_H

typedef ioport volatile unsigned int * DSP5501_REG;
//************************SYSTEM CLOCK**************************
struct DSP5501_PLL
{
 public:
         DSP5501_REG PLLCSR;
         DSP5501_REG CK3SEL;
         DSP5501_REG PLLM;
         DSP5501_REG PLLDIV0;
         DSP5501_REG PLLDIV1;
         DSP5501_REG PLLDIV2;
         DSP5501_REG PLLDIV3;
         DSP5501_REG OSCDIV1;
		 DSP5501_REG WKEN;
		 DSP5501_REG CLKOUTSR;
		 DSP5501_REG CLKMD;

         DSP5501_PLL()//Struct function
         {
	            PLLCSR  =(DSP5501_REG)0X1C80;
		        CK3SEL  =(DSP5501_REG)0X1C82;
		        PLLM    =(DSP5501_REG)0X1C88;
		        PLLDIV0 =(DSP5501_REG)0X1C8A;
		        PLLDIV1 =(DSP5501_REG)0X1C8C;
		        PLLDIV2 =(DSP5501_REG)0X1C8E;
		        PLLDIV3 =(DSP5501_REG)0X1C90;
		        OSCDIV1 =(DSP5501_REG)0X1C92;
		        WKEN    =(DSP5501_REG)0X1C98;
		        CLKOUTSR=(DSP5501_REG)0X8400;
		        CLKMD   =(DSP5501_REG)0X8C00;
         } 
};
//************************ EMIF **************************
struct DSP5501_EMIF
{
   public:
          DSP5501_REG  EGCR1;
		  DSP5501_REG  EGCR2;
		  DSP5501_REG  CE1SCR1;
		  DSP5501_REG  CE1SCR2;
		  DSP5501_REG  CE0SCR1;
		  DSP5501_REG  CE0SCR2;
		  DSP5501_REG  CE2SCR1;
		  DSP5501_REG  CE2SCR2;
		  DSP5501_REG  CE3SCR1;
		  DSP5501_REG  CE3SCR2;
		  DSP5501_REG  SDCR1;
		  DSP5501_REG  SDCR2;
		  DSP5501_REG  SDRCR1;
		  DSP5501_REG  SDRCR2;
		  DSP5501_REG  SDER1;
		  DSP5501_REG  SDER2;
		  DSP5501_REG  CE1SEC1;
		  DSP5501_REG  CE1SEC2;
		  DSP5501_REG  CE0SEC1;
		  DSP5501_REG  CE0SEC2;
		  DSP5501_REG  CE2SEC1;
		  DSP5501_REG  CE2SEC2;
		  DSP5501_REG  CE3SEC1;
		  DSP5501_REG  CE3SEC2;
		  DSP5501_REG  CESIZE1;
		  DSP5501_REG  CESIZE2;
		  DSP5501_EMIF()
		  {
		      EGCR1   =(DSP5501_REG)0X0800;
		      EGCR2   =(DSP5501_REG)0X0801;
		      CE1SCR1 =(DSP5501_REG)0X0802;
		      CE1SCR2 =(DSP5501_REG)0X0803;
		      CE0SCR1 =(DSP5501_REG)0X0804;
		      CE0SCR2 =(DSP5501_REG)0X0805;
		      CE2SCR1 =(DSP5501_REG)0X0808;
		      CE2SCR2 =(DSP5501_REG)0X0809;
		      CE3SCR1 =(DSP5501_REG)0X080A;
		      CE3SCR2 =(DSP5501_REG)0X080B;
		      SDCR1   =(DSP5501_REG)0X080C;
		      SDCR2   =(DSP5501_REG)0X080D;
		      SDRCR1  =(DSP5501_REG)0X080E;
		      SDRCR2  =(DSP5501_REG)0X080F;
		      SDER1   =(DSP5501_REG)0X0810;
		      SDER2   =(DSP5501_REG)0X0811;
		      CE1SEC1 =(DSP5501_REG)0X0822;
		      CE1SEC2 =(DSP5501_REG)0X0823;
		      CE0SEC1 =(DSP5501_REG)0X0823;
		      CE0SEC2 =(DSP5501_REG)0X0825;
		      CE2SEC1 =(DSP5501_REG)0X0828;
		      CE2SEC2 =(DSP5501_REG)0X0829;
		      CE3SEC1 =(DSP5501_REG)0X082A;
		      CE3SEC2 =(DSP5501_REG)0X082B;
		      CESIZE1 =(DSP5501_REG)0X0840;
		      CESIZE2 =(DSP5501_REG)0X0841;
		  }
		  void fnSetCe0Sdram()
		  {   
		     *EGCR1=0x27bc;
				//0x27 No USE
				//b hold disable
					//ECLKOUT1 is driven with value specified by EKnEN during Hold/Reset
					//ECLKOUT1 is enabled
					//Reserved
				//0 No USE
   		     *EGCR2=0x8;
				//0x8 Frequency of ECLKOUT2 is one-fourth of EMIF clock
					//ECLKOUT2 is driven with value specified by EKnEN
					//ECLKOUT2 disabled
   		     *CE0SCR1=0x8432;
				//Turn-Around time=2
				//READ STROBE     =4
				//MTYPE           =32BitWide SDRAM
				//WRITE HOLD MSB  =0
				//READ HOLD       =2
   		     *CE0SCR2=0x2123;
				//WRITE SETUP     =2
				//WRITE STROBE    =4
				//WRITE HOLD      =2
				//READ SETUP      =3				

//*********************************************************
//我只能给一个片选4MByte的SDRAM了
/*   		     *CE1SCR1=0x8432;
				//Turn-Around time=2
				//READ STROBE     =4
				//MTYPE           =32BitWide SDRAM
				//WRITE HOLD MSB  =0
				//READ HOLD       =2
   		     *CE1SCR2=0x2123;
				//WRITE SETUP     =2
				//WRITE STROBE    =4
				//WRITE HOLD      =2
				//READ SETUP      =3*/
//************************************************************				
								
   		     *SDCR1=0x5000;
				//TRC     =5
				//SLFRFR  =Self-refresh mode disabled
   		     *SDCR2=0x4622;
				//SDWTH=4 banks 11Row Address Pins 8Column Address Pins
				//RFEN =SDRAM refresh enabled
				//INIT=No effect
				//TRCD=2
				//TRP =2
   		     *SDRCR1=0x700;
				//PERIOD=0x700 cycles
   		     *SDRCR2=0x100;
				//Extra Refreshes=1
			 *SDER1=0xb8b7;
				//R2WDQM=1
				//RD2WR=3
				//RD2DEAC=2
				//RD2RD=0
				//THZP =1
				//TWR  =1
				//TRRD =1
				//TRAS =3
				//TCL  =CAS latency=3
   		     *SDER2=0x17;
				//WR2RD=1
				//WR2DEAC=01
				//WR2WR=1
				//R2WDQM=1
   		     *CESIZE1=0x00;
   		     	//CES=CE0: 0x000000-0x3FFFFF
					//CE1: 0x400000-0x7FFFFF
					//CE2: 0x800000-0xBFFFFF
					//CE3: 0xC00000-0xFFFFFF 
		  }
};
#define IVPD        (*( (int *)0x49))
#define IVPH        (*( (int *)0x4A))
#define IER0        (*( (int *)0x00))
#define IER1        (*( (int *)0x45))
#define GPIO_DIR    (*((DSP5501_REG)0x3400))
#define GPIO_DATA   (*((DSP5501_REG)0x3401))
#define FLASHBASEADD (0x200000)

const unsigned int iEntryH=0x0;
const unsigned int iEntryL=0x8d58;



#endif