am29_distribute.v

来自「TMS320VC5502 DSP BootLoad源码 包括CPLD源码」· Verilog 代码 · 共 33 行

module am29_distribute
(clk, dsp_aoe, dsp_awe, dsp_ce, dsp_Am29Ready, am29_aoe, am29_awe, 
am29_ce, am29_busy1, am29_busy2);
input         clk;
input         dsp_aoe;
input         dsp_awe;
input         dsp_ce;
output        dsp_Am29Ready;


output        am29_aoe;
output        am29_awe;
output        am29_ce;
input         am29_busy1;
input         am29_busy2;

reg           dsp_Am29Ready;
        
assign am29_aoe=dsp_aoe;
assign am29_awe=dsp_awe;
assign am29_ce=dsp_ce;

always @(posedge clk)	begin
    if( am29_busy1==1 && am29_busy2==1 )
        dsp_Am29Ready<=1;
    else
        dsp_Am29Ready<=0;
 end



endmodule