led_out.v

来自「TMS320VC5502 DSP BootLoad源码 包括CPLD源码」· Verilog 代码 · 共 28 行

module led_out
(clk, led_1, led_2, led_3);
input         clk;
output        led_1;
output        led_2;
output        led_3;

reg     [20:0]  count;
reg             led_1;
reg             led_2;
reg             led_3;

always @(posedge clk) begin
    if (count==21'b100100110000000000000) 
         led_2<=!led_2;
    if (count==21'b000000100000000000000) 
         led_3<=!led_3;

    if (count==21'b111111110000000000000) begin 
          count<=0;
          led_1<=!led_1;
    end
    else       count<=count+1'b1;
          
end

endmodule