evm5502_cpld.tan.qmsg

TMS320VC5502 DSP BootLoad源码 包括CPLD源码

{ "Info" "ITDB_TH_RESULT" "am29_distribute:inst1\|dsp_Am29Ready~reg0 am29_busy2 clk -2.000 ns register " "Info: th for register am29_distribute:inst1\|dsp_Am29Ready~reg0 (data pin = am29_busy2, clock pin = clk) is -2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.600 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK Pin_87 25 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = Pin_87; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 256 56 224 272 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns am29_distribute:inst1\|dsp_Am29Ready~reg0 2 REG LC11 1 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC11; Fanout = 1; REG Node = 'am29_distribute:inst1\|dsp_Am29Ready~reg0'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.300 ns" { clk am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/am29_distribute.v" "" "" { Text "D:/EVM5502_CPLD/am29_distribute.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "D:/EVM5502_CPLD/am29_distribute.v" "" "" { Text "D:/EVM5502_CPLD/am29_distribute.v" 28 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns am29_busy2 1 PIN Pin_94 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = Pin_94; Fanout = 1; PIN Node = 'am29_busy2'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { am29_busy2 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 480 40 208 496 "am29_busy2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(3.200 ns) 6.900 ns am29_distribute:inst1\|dsp_Am29Ready~reg0 2 REG LC11 1 " "Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 6.900 ns; Loc. = LC11; Fanout = 1; REG Node = 'am29_distribute:inst1\|dsp_Am29Ready~reg0'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "5.500 ns" { am29_busy2 am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/am29_distribute.v" "" "" { Text "D:/EVM5502_CPLD/am29_distribute.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 66.67 % " "Info: Total cell delay = 4.600 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 33.33 % " "Info: Total interconnect delay = 2.300 ns ( 33.33 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "6.900 ns" { am29_busy2 am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "6.900 ns" { am29_busy2 am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk dsp_Am29Ready am29_distribute:inst1\|dsp_Am29Ready~reg0 7.000 ns register " "Info: Minimum tco from clock clk to destination pin dsp_Am29Ready through register am29_distribute:inst1\|dsp_Am29Ready~reg0 is 7.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.600 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK Pin_87 25 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = Pin_87; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 256 56 224 272 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns am29_distribute:inst1\|dsp_Am29Ready~reg0 2 REG LC11 1 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC11; Fanout = 1; REG Node = 'am29_distribute:inst1\|dsp_Am29Ready~reg0'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.300 ns" { clk am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/am29_distribute.v" "" "" { Text "D:/EVM5502_CPLD/am29_distribute.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "D:/EVM5502_CPLD/am29_distribute.v" "" "" { Text "D:/EVM5502_CPLD/am29_distribute.v" 28 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Shortest register pin " "Info: + Shortest register to pin delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns am29_distribute:inst1\|dsp_Am29Ready~reg0 1 REG LC11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC11; Fanout = 1; REG Node = 'am29_distribute:inst1\|dsp_Am29Ready~reg0'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/am29_distribute.v" "" "" { Text "D:/EVM5502_CPLD/am29_distribute.v" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns dsp_Am29Ready 2 PIN Pin_98 0 " "Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = Pin_98; Fanout = 0; PIN Node = 'dsp_Am29Ready'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.800 ns" { am29_distribute:inst1|dsp_Am29Ready~reg0 dsp_Am29Ready } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 400 464 643 416 "dsp_Am29Ready" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.800 ns" { am29_distribute:inst1|dsp_Am29Ready~reg0 dsp_Am29Ready } "NODE_NAME" } } }  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.800 ns" { am29_distribute:inst1|dsp_Am29Ready~reg0 dsp_Am29Ready } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "cry_in clk_out 10.000 ns Shortest " "Info: Shortest tpd from source pin cry_in to destination pin clk_out is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns cry_in 1 PIN Pin_84 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = Pin_84; Fanout = 1; PIN Node = 'cry_in'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { cry_in } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 152 80 248 168 "cry_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(4.500 ns) 8.200 ns cry_in~1 2 COMB LC64 1 " "Info: 2: + IC(2.300 ns) + CELL(4.500 ns) = 8.200 ns; Loc. = LC64; Fanout = 1; COMB Node = 'cry_in~1'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "6.800 ns" { cry_in cry_in~1 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 152 80 248 168 "cry_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 10.000 ns clk_out 3 PIN Pin_85 0 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 10.000 ns; Loc. = Pin_85; Fanout = 0; PIN Node = 'clk_out'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.800 ns" { cry_in~1 clk_out } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 152 368 544 168 "clk_out" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.700 ns 77.00 % " "Info: Total cell delay = 7.700 ns ( 77.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 23.00 % " "Info: Total interconnect delay = 2.300 ns ( 23.00 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "10.000 ns" { cry_in cry_in~1 clk_out } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 31 13:01:27 2006 " "Info: Processing ended: Wed May 31 13:01:27 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}