evm5502_cpld.tan.qmsg

TMS320VC5502 DSP BootLoad源码 包括CPLD源码

{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 256 56 224 272 "clk" "" } } } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register led_out:inst\|lpm_counter:count_rtl_0\|dffs\[0\] register led_out:inst\|lpm_counter:count_rtl_0\|dffs\[20\] 71.43 MHz 14.0 ns Internal " "Info: Clock clk has Internal fmax of 71.43 MHz between source register led_out:inst\|lpm_counter:count_rtl_0\|dffs\[0\] and destination register led_out:inst\|lpm_counter:count_rtl_0\|dffs\[20\] (period= 14.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.500 ns + Longest register register " "Info: + Longest register to register delay is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_out:inst\|lpm_counter:count_rtl_0\|dffs\[0\] 1 REG LC50 34 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC50; Fanout = 34; REG Node = 'led_out:inst\|lpm_counter:count_rtl_0\|dffs\[0\]'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { led_out:inst|lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(3.900 ns) 6.300 ns led_out:inst\|i~10sexp 2 COMB SEXP49 8 " "Info: 2: + IC(2.400 ns) + CELL(3.900 ns) = 6.300 ns; Loc. = SEXP49; Fanout = 8; COMB Node = 'led_out:inst\|i~10sexp'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "6.300 ns" { led_out:inst|lpm_counter:count_rtl_0|dffs[0] led_out:inst|i~10sexp } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.200 ns) 9.500 ns led_out:inst\|lpm_counter:count_rtl_0\|dffs\[20\] 3 REG LC60 14 " "Info: 3: + IC(0.000 ns) + CELL(3.200 ns) = 9.500 ns; Loc. = LC60; Fanout = 14; REG Node = 'led_out:inst\|lpm_counter:count_rtl_0\|dffs\[20\]'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.200 ns" { led_out:inst|i~10sexp led_out:inst|lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.100 ns 74.74 % " "Info: Total cell delay = 7.100 ns ( 74.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns 25.26 % " "Info: Total interconnect delay = 2.400 ns ( 25.26 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "9.500 ns" { led_out:inst|lpm_counter:count_rtl_0|dffs[0] led_out:inst|i~10sexp led_out:inst|lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.600 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK Pin_87 25 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = Pin_87; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 256 56 224 272 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns led_out:inst\|lpm_counter:count_rtl_0\|dffs\[20\] 2 REG LC60 14 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC60; Fanout = 14; REG Node = 'led_out:inst\|lpm_counter:count_rtl_0\|dffs\[20\]'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.300 ns" { clk led_out:inst|lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk led_out:inst|lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.600 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK Pin_87 25 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = Pin_87; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 256 56 224 272 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns led_out:inst\|lpm_counter:count_rtl_0\|dffs\[0\] 2 REG LC50 34 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC50; Fanout = 34; REG Node = 'led_out:inst\|lpm_counter:count_rtl_0\|dffs\[0\]'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.300 ns" { clk led_out:inst|lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk led_out:inst|lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } }  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk led_out:inst|lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } } } { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk led_out:inst|lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "9.500 ns" { led_out:inst|lpm_counter:count_rtl_0|dffs[0] led_out:inst|i~10sexp led_out:inst|lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } } } { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk led_out:inst|lpm_counter:count_rtl_0|dffs[20] } "NODE_NAME" } } } { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk led_out:inst|lpm_counter:count_rtl_0|dffs[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "am29_distribute:inst1\|dsp_Am29Ready~reg0 am29_busy2 clk 6.200 ns register " "Info: tsu for register am29_distribute:inst1\|dsp_Am29Ready~reg0 (data pin = am29_busy2, clock pin = clk) is 6.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns + Longest pin register " "Info: + Longest pin to register delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns am29_busy2 1 PIN Pin_94 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = Pin_94; Fanout = 1; PIN Node = 'am29_busy2'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { am29_busy2 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 480 40 208 496 "am29_busy2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(3.200 ns) 6.900 ns am29_distribute:inst1\|dsp_Am29Ready~reg0 2 REG LC11 1 " "Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 6.900 ns; Loc. = LC11; Fanout = 1; REG Node = 'am29_distribute:inst1\|dsp_Am29Ready~reg0'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "5.500 ns" { am29_busy2 am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/am29_distribute.v" "" "" { Text "D:/EVM5502_CPLD/am29_distribute.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 66.67 % " "Info: Total cell delay = 4.600 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 33.33 % " "Info: Total interconnect delay = 2.300 ns ( 33.33 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "6.900 ns" { am29_busy2 am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "D:/EVM5502_CPLD/am29_distribute.v" "" "" { Text "D:/EVM5502_CPLD/am29_distribute.v" 28 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.600 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK Pin_87 25 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = Pin_87; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 256 56 224 272 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns am29_distribute:inst1\|dsp_Am29Ready~reg0 2 REG LC11 1 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC11; Fanout = 1; REG Node = 'am29_distribute:inst1\|dsp_Am29Ready~reg0'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.300 ns" { clk am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/am29_distribute.v" "" "" { Text "D:/EVM5502_CPLD/am29_distribute.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "6.900 ns" { am29_busy2 am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk am29_distribute:inst1|dsp_Am29Ready~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led_2 led_out:inst\|led_2~reg0 7.000 ns register " "Info: tco from clock clk to destination pin led_2 through register led_out:inst\|led_2~reg0 is 7.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.600 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK Pin_87 25 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = Pin_87; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 256 56 224 272 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns led_out:inst\|led_2~reg0 2 REG LC58 2 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC58; Fanout = 2; REG Node = 'led_out:inst\|led_2~reg0'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.300 ns" { clk led_out:inst|led_2~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/led_out.v" "" "" { Text "D:/EVM5502_CPLD/led_out.v" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk led_out:inst|led_2~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "D:/EVM5502_CPLD/led_out.v" "" "" { Text "D:/EVM5502_CPLD/led_out.v" 25 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register pin " "Info: + Longest register to pin delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_out:inst\|led_2~reg0 1 REG LC58 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC58; Fanout = 2; REG Node = 'led_out:inst\|led_2~reg0'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { led_out:inst|led_2~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/led_out.v" "" "" { Text "D:/EVM5502_CPLD/led_out.v" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns led_2 2 PIN Pin_76 0 " "Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = Pin_76; Fanout = 0; PIN Node = 'led_2'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.800 ns" { led_out:inst|led_2~reg0 led_2 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 272 360 536 288 "led_2" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.800 ns" { led_out:inst|led_2~reg0 led_2 } "NODE_NAME" } } }  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "3.600 ns" { clk led_out:inst|led_2~reg0 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.800 ns" { led_out:inst|led_2~reg0 led_2 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "dsp_aoe am29_aoe 10.000 ns Longest " "Info: Longest tpd from source pin dsp_aoe to destination pin am29_aoe is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns dsp_aoe 1 PIN Pin_40 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = Pin_40; Fanout = 1; PIN Node = 'dsp_aoe'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "" { dsp_aoe } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 416 40 208 432 "dsp_aoe" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(4.500 ns) 8.200 ns dsp_aoe~1 2 COMB LC7 1 " "Info: 2: + IC(2.300 ns) + CELL(4.500 ns) = 8.200 ns; Loc. = LC7; Fanout = 1; COMB Node = 'dsp_aoe~1'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "6.800 ns" { dsp_aoe dsp_aoe~1 } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 416 40 208 432 "dsp_aoe" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 10.000 ns am29_aoe 3 PIN Pin_6 0 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 10.000 ns; Loc. = Pin_6; Fanout = 0; PIN Node = 'am29_aoe'" {  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "1.800 ns" { dsp_aoe~1 am29_aoe } "NODE_NAME" } } } { "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" "" "" { Schematic "D:/EVM5502_CPLD/EVM5502_CPLD.bdf" { { 416 464 640 432 "am29_aoe" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.700 ns 77.00 % " "Info: Total cell delay = 7.700 ns ( 77.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 23.00 % " "Info: Total interconnect delay = 2.300 ns ( 23.00 % )" {  } {  } 0}  } { { "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" "" "" { Report "D:/EVM5502_CPLD/db/EVM5502_CPLD_cmp.qrpt" Compiler "EVM5502_CPLD" "UNKNOWN" "V1" "D:/EVM5502_CPLD/db/EVM5502_CPLD.quartus_db" { Floorplan "" "" "10.000 ns" { dsp_aoe dsp_aoe~1 am29_aoe } "NODE_NAME" } } }  } 0}