evm5502_cpld.tan.rpt

TMS320VC5502 DSP BootLoad源码 包括CPLD源码

; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                      ; From                                         ; To                                            ;
+------------------------+-------+---------------+----------------------------------+----------------------------------------------+-----------------------------------------------+
; Worst-case tsu         ; N/A   ; None          ; 6.200 ns                         ; am29_busy1                                   ; am29_distribute:inst1|dsp_Am29Ready~reg0      ;
; Worst-case tco         ; N/A   ; None          ; 7.000 ns                         ; am29_distribute:inst1|dsp_Am29Ready~reg0     ; dsp_Am29Ready                                 ;
; Worst-case tpd         ; N/A   ; None          ; 10.000 ns                        ; cry_in                                       ; clk_out                                       ;
; Worst-case th          ; N/A   ; None          ; -2.000 ns                        ; am29_busy1                                   ; am29_distribute:inst1|dsp_Am29Ready~reg0      ;
; Worst-case minimum tco ; N/A   ; None          ; 7.000 ns                         ; am29_distribute:inst1|dsp_Am29Ready~reg0     ; dsp_Am29Ready                                 ;
; Worst-case minimum tpd ; N/A   ; None          ; 10.000 ns                        ; cry_in                                       ; clk_out                                       ;
; Clock Setup: 'clk'     ; N/A   ; None          ; 71.43 MHz ( period = 14.000 ns ) ; led_out:inst|lpm_counter:count_rtl_0|dffs[1] ; led_out:inst|lpm_counter:count_rtl_0|dffs[19] ;
+------------------------+-------+---------------+----------------------------------+----------------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                               ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack                                   ; Actual fmax (period)                                       ; From                                          ; To                                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+-----------------------------------------------+-----------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[0]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[20] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[8]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[20] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[7]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[20] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[6]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[20] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[5]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[20] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[4]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[20] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[3]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[20] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[2]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[20] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[1]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[20] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[0]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[13] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[8]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[13] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[7]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[13] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[6]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[13] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[5]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[13] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[4]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[13] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                           ; led_out:inst|lpm_counter:count_rtl_0|dffs[3]  ; led_out:inst|lpm_counter:count_rtl_0|dffs[13] ; clk        ; clk      ; None                        ; None                      ; None                    ;