prev_cmp_new_pwm.fit.qmsg

一个PWM参数器

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.268 ns register register " "Info: Estimated most critical path is register to register delay of 3.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[0\] 1 REG LAB_X25_Y8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y8; Fanout = 4; REG Node = 'counter\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[0] } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.414 ns) 1.060 ns LessThan0~157 2 COMB LAB_X26_Y8 1 " "Info: 2: + IC(0.646 ns) + CELL(0.414 ns) = 1.060 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~157'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.060 ns" { counter[0] LessThan0~157 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.131 ns LessThan0~159 3 COMB LAB_X26_Y8 1 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.131 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~159'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~157 LessThan0~159 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.202 ns LessThan0~161 4 COMB LAB_X26_Y8 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.202 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~161'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~159 LessThan0~161 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.273 ns LessThan0~163 5 COMB LAB_X26_Y8 1 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.273 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~163'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~161 LessThan0~163 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.344 ns LessThan0~165 6 COMB LAB_X26_Y8 1 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.344 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~165'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~163 LessThan0~165 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.415 ns LessThan0~167 7 COMB LAB_X26_Y8 1 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.415 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~167'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~165 LessThan0~167 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.486 ns LessThan0~169 8 COMB LAB_X26_Y8 1 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.486 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~169'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~167 LessThan0~169 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.557 ns LessThan0~171 9 COMB LAB_X26_Y8 1 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.557 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~171'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~169 LessThan0~171 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.628 ns LessThan0~173 10 COMB LAB_X26_Y8 1 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.628 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~173'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~171 LessThan0~173 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.699 ns LessThan0~175 11 COMB LAB_X26_Y8 1 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.699 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~175'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~173 LessThan0~175 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.770 ns LessThan0~177 12 COMB LAB_X26_Y8 1 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.770 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~177'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~175 LessThan0~177 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.180 ns LessThan0~178 13 COMB LAB_X26_Y8 1 " "Info: 13: + IC(0.000 ns) + CELL(0.410 ns) = 2.180 ns; Loc. = LAB_X26_Y8; Fanout = 1; COMB Node = 'LessThan0~178'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { LessThan0~177 LessThan0~178 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.606 ns) + CELL(0.398 ns) 3.184 ns PwmOut~2 14 COMB LAB_X26_Y9 1 " "Info: 14: + IC(0.606 ns) + CELL(0.398 ns) = 3.184 ns; Loc. = LAB_X26_Y9; Fanout = 1; COMB Node = 'PwmOut~2'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.004 ns" { LessThan0~178 PwmOut~2 } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.268 ns PwmOut~reg0 15 REG LAB_X26_Y9 1 " "Info: 15: + IC(0.000 ns) + CELL(0.084 ns) = 3.268 ns; Loc. = LAB_X26_Y9; Fanout = 1; REG Node = 'PwmOut~reg0'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { PwmOut~2 PwmOut~reg0 } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.016 ns ( 61.69 % ) " "Info: Total cell delay = 2.016 ns ( 61.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.252 ns ( 38.31 % ) " "Info: Total interconnect delay = 1.252 ns ( 38.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.268 ns" { counter[0] LessThan0~157 LessThan0~159 LessThan0~161 LessThan0~163 LessThan0~165 LessThan0~167 LessThan0~169 LessThan0~171 LessThan0~173 LessThan0~175 LessThan0~177 LessThan0~178 PwmOut~2 PwmOut~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X14_Y0 X28_Y14 " "Info: The peak interconnect region extends from location X14_Y0 to location X28_Y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PwmOut 0 " "Info: Pin \"PwmOut\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/mywork/new_pwm/new_pwm.fit.smsg " "Info: Generated suppressed messages file E:/mywork/new_pwm/new_pwm.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "181 " "Info: Allocated 181 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 21 10:19:13 2007 " "Info: Processing ended: Sun Oct 21 10:19:13 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}