📄 prev_cmp_new_pwm.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter\[0\] register PwmOut~reg0 304.51 MHz 3.284 ns Internal " "Info: Clock \"clk\" has Internal fmax of 304.51 MHz between source register \"counter\[0\]\" and destination register \"PwmOut~reg0\" (period= 3.284 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.076 ns + Longest register register " "Info: + Longest register to register delay is 3.076 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[0\] 1 REG LCFF_X25_Y8_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y8_N9; Fanout = 4; REG Node = 'counter\[0\]'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[0] } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.512 ns) + CELL(0.414 ns) 0.926 ns LessThan0~157 2 COMB LCCOMB_X26_Y8_N0 1 " "Info: 2: + IC(0.512 ns) + CELL(0.414 ns) = 0.926 ns; Loc. = LCCOMB_X26_Y8_N0; Fanout = 1; COMB Node = 'LessThan0~157'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.926 ns" { counter[0] LessThan0~157 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.997 ns LessThan0~159 3 COMB LCCOMB_X26_Y8_N2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.997 ns; Loc. = LCCOMB_X26_Y8_N2; Fanout = 1; COMB Node = 'LessThan0~159'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~157 LessThan0~159 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.068 ns LessThan0~161 4 COMB LCCOMB_X26_Y8_N4 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.068 ns; Loc. = LCCOMB_X26_Y8_N4; Fanout = 1; COMB Node = 'LessThan0~161'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~159 LessThan0~161 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.139 ns LessThan0~163 5 COMB LCCOMB_X26_Y8_N6 1 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.139 ns; Loc. = LCCOMB_X26_Y8_N6; Fanout = 1; COMB Node = 'LessThan0~163'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~161 LessThan0~163 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.210 ns LessThan0~165 6 COMB LCCOMB_X26_Y8_N8 1 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.210 ns; Loc. = LCCOMB_X26_Y8_N8; Fanout = 1; COMB Node = 'LessThan0~165'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~163 LessThan0~165 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.281 ns LessThan0~167 7 COMB LCCOMB_X26_Y8_N10 1 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.281 ns; Loc. = LCCOMB_X26_Y8_N10; Fanout = 1; COMB Node = 'LessThan0~167'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~165 LessThan0~167 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.352 ns LessThan0~169 8 COMB LCCOMB_X26_Y8_N12 1 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.352 ns; Loc. = LCCOMB_X26_Y8_N12; Fanout = 1; COMB Node = 'LessThan0~169'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~167 LessThan0~169 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.511 ns LessThan0~171 9 COMB LCCOMB_X26_Y8_N14 1 " "Info: 9: + IC(0.000 ns) + CELL(0.159 ns) = 1.511 ns; Loc. = LCCOMB_X26_Y8_N14; Fanout = 1; COMB Node = 'LessThan0~171'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { LessThan0~169 LessThan0~171 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.582 ns LessThan0~173 10 COMB LCCOMB_X26_Y8_N16 1 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.582 ns; Loc. = LCCOMB_X26_Y8_N16; Fanout = 1; COMB Node = 'LessThan0~173'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~171 LessThan0~173 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.653 ns LessThan0~175 11 COMB LCCOMB_X26_Y8_N18 1 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.653 ns; Loc. = LCCOMB_X26_Y8_N18; Fanout = 1; COMB Node = 'LessThan0~175'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~173 LessThan0~175 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.724 ns LessThan0~177 12 COMB LCCOMB_X26_Y8_N20 1 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.724 ns; Loc. = LCCOMB_X26_Y8_N20; Fanout = 1; COMB Node = 'LessThan0~177'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~175 LessThan0~177 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.134 ns LessThan0~178 13 COMB LCCOMB_X26_Y8_N22 1 " "Info: 13: + IC(0.000 ns) + CELL(0.410 ns) = 2.134 ns; Loc. = LCCOMB_X26_Y8_N22; Fanout = 1; COMB Node = 'LessThan0~178'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { LessThan0~177 LessThan0~178 } "NODE_NAME" } } { "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.708 ns) + CELL(0.150 ns) 2.992 ns PwmOut~2 14 COMB LCCOMB_X26_Y9_N0 1 " "Info: 14: + IC(0.708 ns) + CELL(0.150 ns) = 2.992 ns; Loc. = LCCOMB_X26_Y9_N0; Fanout = 1; COMB Node = 'PwmOut~2'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.858 ns" { LessThan0~178 PwmOut~2 } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.076 ns PwmOut~reg0 15 REG LCFF_X26_Y9_N1 1 " "Info: 15: + IC(0.000 ns) + CELL(0.084 ns) = 3.076 ns; Loc. = LCFF_X26_Y9_N1; Fanout = 1; REG Node = 'PwmOut~reg0'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { PwmOut~2 PwmOut~reg0 } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.856 ns ( 60.34 % ) " "Info: Total cell delay = 1.856 ns ( 60.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.220 ns ( 39.66 % ) " "Info: Total interconnect delay = 1.220 ns ( 39.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.076 ns" { counter[0] LessThan0~157 LessThan0~159 LessThan0~161 LessThan0~163 LessThan0~165 LessThan0~167 LessThan0~169 LessThan0~171 LessThan0~173 LessThan0~175 LessThan0~177 LessThan0~178 PwmOut~2 PwmOut~reg0 } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.076 ns" { counter[0] LessThan0~157 LessThan0~159 LessThan0~161 LessThan0~163 LessThan0~165 LessThan0~167 LessThan0~169 LessThan0~171 LessThan0~173 LessThan0~175 LessThan0~177 LessThan0~178 PwmOut~2 PwmOut~reg0 } { 0.000ns 0.512ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.708ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.006 ns - Smallest " "Info: - Smallest clock skew is 0.006 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.370 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.370 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 37 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 37; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.537 ns) 2.370 ns PwmOut~reg0 3 REG LCFF_X26_Y9_N1 1 " "Info: 3: + IC(0.722 ns) + CELL(0.537 ns) = 2.370 ns; Loc. = LCFF_X26_Y9_N1; Fanout = 1; REG Node = 'PwmOut~reg0'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { clk~clkctrl PwmOut~reg0 } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.39 % ) " "Info: Total cell delay = 1.526 ns ( 64.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.844 ns ( 35.61 % ) " "Info: Total interconnect delay = 0.844 ns ( 35.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.370 ns" { clk clk~clkctrl PwmOut~reg0 } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.370 ns" { clk clk~combout clk~clkctrl PwmOut~reg0 } { 0.000ns 0.000ns 0.122ns 0.722ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.364 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 37 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 37; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.537 ns) 2.364 ns counter\[0\] 3 REG LCFF_X25_Y8_N9 4 " "Info: 3: + IC(0.716 ns) + CELL(0.537 ns) = 2.364 ns; Loc. = LCFF_X25_Y8_N9; Fanout = 4; REG Node = 'counter\[0\]'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.253 ns" { clk~clkctrl counter[0] } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.55 % ) " "Info: Total cell delay = 1.526 ns ( 64.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.838 ns ( 35.45 % ) " "Info: Total interconnect delay = 0.838 ns ( 35.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.364 ns" { clk clk~clkctrl counter[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.364 ns" { clk clk~combout clk~clkctrl counter[0] } { 0.000ns 0.000ns 0.122ns 0.716ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.370 ns" { clk clk~clkctrl PwmOut~reg0 } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.370 ns" { clk clk~combout clk~clkctrl PwmOut~reg0 } { 0.000ns 0.000ns 0.122ns 0.722ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.364 ns" { clk clk~clkctrl counter[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.364 ns" { clk clk~combout clk~clkctrl counter[0] } { 0.000ns 0.000ns 0.122ns 0.716ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.076 ns" { counter[0] LessThan0~157 LessThan0~159 LessThan0~161 LessThan0~163 LessThan0~165 LessThan0~167 LessThan0~169 LessThan0~171 LessThan0~173 LessThan0~175 LessThan0~177 LessThan0~178 PwmOut~2 PwmOut~reg0 } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.076 ns" { counter[0] LessThan0~157 LessThan0~159 LessThan0~161 LessThan0~163 LessThan0~165 LessThan0~167 LessThan0~169 LessThan0~171 LessThan0~173 LessThan0~175 LessThan0~177 LessThan0~178 PwmOut~2 PwmOut~reg0 } { 0.000ns 0.512ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.708ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.084ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.370 ns" { clk clk~clkctrl PwmOut~reg0 } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.370 ns" { clk clk~combout clk~clkctrl PwmOut~reg0 } { 0.000ns 0.000ns 0.122ns 0.722ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.364 ns" { clk clk~clkctrl counter[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.364 ns" { clk clk~combout clk~clkctrl counter[0] } { 0.000ns 0.000ns 0.122ns 0.716ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "duty\[0\] wr_en clk 4.999 ns register " "Info: tsu for register \"duty\[0\]\" (data pin = \"wr_en\", clock pin = \"clk\") is 4.999 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.399 ns + Longest pin register " "Info: + Longest pin to register delay is 7.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns wr_en 1 PIN PIN_96 2 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_96; Fanout = 2; PIN Node = 'wr_en'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_en } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.987 ns) + CELL(0.275 ns) 6.104 ns duty\[11\]~411 2 COMB LCCOMB_X24_Y8_N10 12 " "Info: 2: + IC(4.987 ns) + CELL(0.275 ns) = 6.104 ns; Loc. = LCCOMB_X24_Y8_N10; Fanout = 12; COMB Node = 'duty\[11\]~411'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.262 ns" { wr_en duty[11]~411 } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.635 ns) + CELL(0.660 ns) 7.399 ns duty\[0\] 3 REG LCFF_X26_Y8_N1 1 " "Info: 3: + IC(0.635 ns) + CELL(0.660 ns) = 7.399 ns; Loc. = LCFF_X26_Y8_N1; Fanout = 1; REG Node = 'duty\[0\]'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.295 ns" { duty[11]~411 duty[0] } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.777 ns ( 24.02 % ) " "Info: Total cell delay = 1.777 ns ( 24.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.622 ns ( 75.98 % ) " "Info: Total interconnect delay = 5.622 ns ( 75.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.399 ns" { wr_en duty[11]~411 duty[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.399 ns" { wr_en wr_en~combout duty[11]~411 duty[0] } { 0.000ns 0.000ns 4.987ns 0.635ns } { 0.000ns 0.842ns 0.275ns 0.660ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.364 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 37 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 37; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.537 ns) 2.364 ns duty\[0\] 3 REG LCFF_X26_Y8_N1 1 " "Info: 3: + IC(0.716 ns) + CELL(0.537 ns) = 2.364 ns; Loc. = LCFF_X26_Y8_N1; Fanout = 1; REG Node = 'duty\[0\]'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.253 ns" { clk~clkctrl duty[0] } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.55 % ) " "Info: Total cell delay = 1.526 ns ( 64.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.838 ns ( 35.45 % ) " "Info: Total interconnect delay = 0.838 ns ( 35.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.364 ns" { clk clk~clkctrl duty[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.364 ns" { clk clk~combout clk~clkctrl duty[0] } { 0.000ns 0.000ns 0.122ns 0.716ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.399 ns" { wr_en duty[11]~411 duty[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.399 ns" { wr_en wr_en~combout duty[11]~411 duty[0] } { 0.000ns 0.000ns 4.987ns 0.635ns } { 0.000ns 0.842ns 0.275ns 0.660ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.364 ns" { clk clk~clkctrl duty[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.364 ns" { clk clk~combout clk~clkctrl duty[0] } { 0.000ns 0.000ns 0.122ns 0.716ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk PwmOut PwmOut~reg0 6.383 ns register " "Info: tco from clock \"clk\" to destination pin \"PwmOut\" through register \"PwmOut~reg0\" is 6.383 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.370 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.370 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 37 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 37; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.537 ns) 2.370 ns PwmOut~reg0 3 REG LCFF_X26_Y9_N1 1 " "Info: 3: + IC(0.722 ns) + CELL(0.537 ns) = 2.370 ns; Loc. = LCFF_X26_Y9_N1; Fanout = 1; REG Node = 'PwmOut~reg0'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { clk~clkctrl PwmOut~reg0 } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.39 % ) " "Info: Total cell delay = 1.526 ns ( 64.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.844 ns ( 35.61 % ) " "Info: Total interconnect delay = 0.844 ns ( 35.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.370 ns" { clk clk~clkctrl PwmOut~reg0 } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.370 ns" { clk clk~combout clk~clkctrl PwmOut~reg0 } { 0.000ns 0.000ns 0.122ns 0.722ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.763 ns + Longest register pin " "Info: + Longest register to pin delay is 3.763 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PwmOut~reg0 1 REG LCFF_X26_Y9_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y9_N1; Fanout = 1; REG Node = 'PwmOut~reg0'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PwmOut~reg0 } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 38 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.965 ns) + CELL(2.798 ns) 3.763 ns PwmOut 2 PIN PIN_119 0 " "Info: 2: + IC(0.965 ns) + CELL(2.798 ns) = 3.763 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'PwmOut'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.763 ns" { PwmOut~reg0 PwmOut } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 74.36 % ) " "Info: Total cell delay = 2.798 ns ( 74.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.965 ns ( 25.64 % ) " "Info: Total interconnect delay = 0.965 ns ( 25.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.763 ns" { PwmOut~reg0 PwmOut } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.763 ns" { PwmOut~reg0 PwmOut } { 0.000ns 0.965ns } { 0.000ns 2.798ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.370 ns" { clk clk~clkctrl PwmOut~reg0 } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.370 ns" { clk clk~combout clk~clkctrl PwmOut~reg0 } { 0.000ns 0.000ns 0.122ns 0.722ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.763 ns" { PwmOut~reg0 PwmOut } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.763 ns" { PwmOut~reg0 PwmOut } { 0.000ns 0.965ns } { 0.000ns 2.798ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "period\[5\] wrData\[5\] clk 0.570 ns register " "Info: th for register \"period\[5\]\" (data pin = \"wrData\[5\]\", clock pin = \"clk\") is 0.570 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.363 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.363 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 37 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 37; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.715 ns) + CELL(0.537 ns) 2.363 ns period\[5\] 3 REG LCFF_X24_Y8_N13 1 " "Info: 3: + IC(0.715 ns) + CELL(0.537 ns) = 2.363 ns; Loc. = LCFF_X24_Y8_N13; Fanout = 1; REG Node = 'period\[5\]'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.252 ns" { clk~clkctrl period[5] } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.58 % ) " "Info: Total cell delay = 1.526 ns ( 64.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.837 ns ( 35.42 % ) " "Info: Total interconnect delay = 0.837 ns ( 35.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { clk clk~clkctrl period[5] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.363 ns" { clk clk~combout clk~clkctrl period[5] } { 0.000ns 0.000ns 0.122ns 0.715ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" { } { { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.059 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns wrData\[5\] 1 PIN PIN_89 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_89; Fanout = 2; PIN Node = 'wrData\[5\]'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrData[5] } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.149 ns) 1.975 ns period\[5\]~feeder 2 COMB LCCOMB_X24_Y8_N12 1 " "Info: 2: + IC(0.827 ns) + CELL(0.149 ns) = 1.975 ns; Loc. = LCCOMB_X24_Y8_N12; Fanout = 1; COMB Node = 'period\[5\]~feeder'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.976 ns" { wrData[5] period[5]~feeder } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.059 ns period\[5\] 3 REG LCFF_X24_Y8_N13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.059 ns; Loc. = LCFF_X24_Y8_N13; Fanout = 1; REG Node = 'period\[5\]'" { } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { period[5]~feeder period[5] } "NODE_NAME" } } { "new_pwm.vhd" "" { Text "E:/mywork/new_pwm/new_pwm.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.232 ns ( 59.83 % ) " "Info: Total cell delay = 1.232 ns ( 59.83 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.827 ns ( 40.17 % ) " "Info: Total interconnect delay = 0.827 ns ( 40.17 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.059 ns" { wrData[5] period[5]~feeder period[5] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.059 ns" { wrData[5] wrData[5]~combout period[5]~feeder period[5] } { 0.000ns 0.000ns 0.827ns 0.000ns } { 0.000ns 0.999ns 0.149ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { clk clk~clkctrl period[5] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.363 ns" { clk clk~combout clk~clkctrl period[5] } { 0.000ns 0.000ns 0.122ns 0.715ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.059 ns" { wrData[5] period[5]~feeder period[5] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.059 ns" { wrData[5] wrData[5]~combout period[5]~feeder period[5] } { 0.000ns 0.000ns 0.827ns 0.000ns } { 0.000ns 0.999ns 0.149ns 0.084ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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