new_pwm.vho

一个PWM参数器

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

-- DATE "10/21/2007 10:19:21"

-- 
-- Device: Altera EP2C5T144C6 Package TQFP144
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	new_pwm IS
    PORT (
	clk : IN std_logic;
	wr_en : IN std_logic;
	addr : IN std_logic;
	wrData : IN std_logic_vector(11 DOWNTO 0);
	PwmOut : OUT std_logic
	);
END new_pwm;

ARCHITECTURE structure OF new_pwm IS
SIGNAL GNDs : std_logic_vector(2048 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(2048 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_wr_en : std_logic;
SIGNAL ww_addr : std_logic;
SIGNAL ww_wrData : std_logic_vector(11 DOWNTO 0);
SIGNAL ww_PwmOut : std_logic;
SIGNAL \clk~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[1]~134_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[1]~134_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \clk~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \clk~clkctrl_modesel\ : std_logic;
SIGNAL \wrData[11]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \wr_en~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \addr~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \duty[11]~411_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \duty[11]~411_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \counter[0]~133_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[0]~133_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wrData[0]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \period[0]~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \period[0]~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \period[11]~404_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \period[11]~404_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \counter[8]~141_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[8]~141_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wrData[8]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \period[8]~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \period[8]~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \counter[10]~143_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[10]~143_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \counter[11]~132_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[11]~132_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Equal0~108_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Equal0~108_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \counter[2]~135_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[2]~135_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wrData[2]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Equal0~110_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Equal0~110_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \counter[6]~139_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[6]~139_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wrData[6]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \period[6]~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \period[6]~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Equal0~109_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Equal0~109_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Equal0~111_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Equal0~111_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \counter[3]~136_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[3]~136_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wrData[3]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \counter[4]~137_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[4]~137_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \counter[5]~138_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[5]~138_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wrData[5]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \period[5]~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \period[5]~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \counter[7]~140_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[7]~140_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wrData[7]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \period[7]~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \period[7]~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \counter[9]~142_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[9]~142_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wrData[9]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \period[9]~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \period[9]~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wrData[10]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \wrData[4]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \wrData[1]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \LessThan0~157_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~157_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~159_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~159_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~161_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~161_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~163_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~163_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~165_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~165_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~167_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~167_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~169_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~169_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~171_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~171_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~173_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~173_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~175_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~175_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~177_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~177_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan0~178_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan0~178_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \PwmOut~2_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \PwmOut~2_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \PwmOut~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \counter[1]~regout\ : std_logic;
SIGNAL \counter[1]~134_combout\ : std_logic;
SIGNAL \duty[10]~regout\ : std_logic;
SIGNAL \duty[8]~regout\ : std_logic;
SIGNAL \duty[7]~regout\ : std_logic;
SIGNAL \duty[5]~regout\ : std_logic;
SIGNAL \duty[4]~regout\ : std_logic;
SIGNAL \period[1]~regout\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \clk~clkctrl_outclk\ : std_logic;
SIGNAL \wrData[11]~combout\ : std_logic;
SIGNAL \wr_en~combout\ : std_logic;
SIGNAL \addr~combout\ : std_logic;
SIGNAL \duty[11]~411_combout\ : std_logic;
SIGNAL \duty[11]~regout\ : std_logic;
SIGNAL \counter[0]~133_combout\ : std_logic;
SIGNAL \wrData[0]~combout\ : std_logic;
SIGNAL \period[0]~feeder_combout\ : std_logic;
SIGNAL \period[11]~404_combout\ : std_logic;
SIGNAL \period[0]~regout\ : std_logic;
SIGNAL \counter[8]~141_combout\ : std_logic;
SIGNAL \wrData[8]~combout\ : std_logic;
SIGNAL \period[8]~feeder_combout\ : std_logic;
SIGNAL \period[8]~regout\ : std_logic;
SIGNAL \counter[8]~regout\ : std_logic;
SIGNAL \counter[10]~154\ : std_logic;
SIGNAL \counter[11]~132_combout\ : std_logic;
SIGNAL \period[11]~regout\ : std_logic;
SIGNAL \counter[11]~regout\ : std_logic;
SIGNAL \Equal0~108_combout\ : std_logic;
SIGNAL \counter[2]~135_combout\ : std_logic;
SIGNAL \wrData[2]~combout\ : std_logic;
SIGNAL \period[2]~regout\ : std_logic;
SIGNAL \counter[2]~regout\ : std_logic;
SIGNAL \Equal0~110_combout\ : std_logic;
SIGNAL \counter[6]~139_combout\ : std_logic;
SIGNAL \wrData[6]~combout\ : std_logic;
SIGNAL \period[6]~feeder_combout\ : std_logic;
SIGNAL \period[6]~regout\ : std_logic;
SIGNAL \counter[6]~regout\ : std_logic;
SIGNAL \Equal0~109_combout\ : std_logic;
SIGNAL \Equal0~111_combout\ : std_logic;
SIGNAL \counter[0]~regout\ : std_logic;
SIGNAL \counter[0]~144\ : std_logic;
SIGNAL \counter[1]~145\ : std_logic;
SIGNAL \counter[2]~146\ : std_logic;
SIGNAL \counter[3]~136_combout\ : std_logic;
SIGNAL \wrData[3]~combout\ : std_logic;
SIGNAL \period[3]~regout\ : std_logic;
SIGNAL \counter[3]~regout\ : std_logic;
SIGNAL \counter[3]~147\ : std_logic;
SIGNAL \counter[4]~148\ : std_logic;
SIGNAL \counter[5]~138_combout\ : std_logic;
SIGNAL \wrData[5]~combout\ : std_logic;
SIGNAL \period[5]~feeder_combout\ : std_logic;
SIGNAL \period[5]~regout\ : std_logic;
SIGNAL \counter[5]~regout\ : std_logic;
SIGNAL \counter[5]~149\ : std_logic;
SIGNAL \counter[6]~150\ : std_logic;
SIGNAL \counter[7]~140_combout\ : std_logic;
SIGNAL \wrData[7]~combout\ : std_logic;
SIGNAL \period[7]~feeder_combout\ : std_logic;
SIGNAL \period[7]~regout\ : std_logic;
SIGNAL \counter[7]~regout\ : std_logic;
SIGNAL \counter[7]~151\ : std_logic;
SIGNAL \counter[8]~152\ : std_logic;
SIGNAL \counter[9]~142_combout\ : std_logic;
SIGNAL \wrData[9]~combout\ : std_logic;
SIGNAL \period[9]~feeder_combout\ : std_logic;
SIGNAL \period[9]~regout\ : std_logic;
SIGNAL \counter[9]~regout\ : std_logic;
SIGNAL \counter[9]~153\ : std_logic;
SIGNAL \counter[10]~143_combout\ : std_logic;
SIGNAL \wrData[10]~combout\ : std_logic;
SIGNAL \period[10]~regout\ : std_logic;
SIGNAL \counter[10]~regout\ : std_logic;
SIGNAL \duty[9]~regout\ : std_logic;
SIGNAL \duty[6]~regout\ : std_logic;
SIGNAL \counter[4]~137_combout\ : std_logic;
SIGNAL \wrData[4]~combout\ : std_logic;
SIGNAL \period[4]~regout\ : std_logic;
SIGNAL \counter[4]~regout\ : std_logic;
SIGNAL \duty[3]~regout\ : std_logic;
SIGNAL \duty[2]~regout\ : std_logic;
SIGNAL \wrData[1]~combout\ : std_logic;
SIGNAL \duty[1]~regout\ : std_logic;
SIGNAL \duty[0]~regout\ : std_logic;
SIGNAL \LessThan0~157_cout\ : std_logic;
SIGNAL \LessThan0~159_cout\ : std_logic;
SIGNAL \LessThan0~161_cout\ : std_logic;
SIGNAL \LessThan0~163_cout\ : std_logic;
SIGNAL \LessThan0~165_cout\ : std_logic;
SIGNAL \LessThan0~167_cout\ : std_logic;
SIGNAL \LessThan0~169_cout\ : std_logic;
SIGNAL \LessThan0~171_cout\ : std_logic;
SIGNAL \LessThan0~173_cout\ : std_logic;
SIGNAL \LessThan0~175_cout\ : std_logic;
SIGNAL \LessThan0~177_cout\ : std_logic;
SIGNAL \LessThan0~178_combout\ : std_logic;
SIGNAL \PwmOut~2_combout\ : std_logic;
SIGNAL \PwmOut~reg0_regout\ : std_logic;
COMPONENT cycloneii_lcell_comb
PORT (
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;

COMPONENT cycloneii_lcell_ff
PORT (
	clk : IN STD_LOGIC;
	datain : IN STD_LOGIC;
	sdata : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	regout : OUT STD_LOGIC);
END COMPONENT;

COMPONENT cycloneii_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	differentialin : IN STD_LOGIC;
	linkin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	differentialout : OUT STD_LOGIC;
	linkout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(25 DOWNTO 0));
END COMPONENT;

COMPONENT cycloneii_clkctrl
PORT (
	ena : IN STD_LOGIC;
	inclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	clkselect : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	outclk : OUT STD_LOGIC;
	modesel : IN STD_LOGIC);
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_clk <= clk;
ww_wr_en <= wr_en;
ww_addr <= addr;
ww_wrData <= wrData;
PwmOut <= ww_PwmOut;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\counter[1]~134_modesel\ <= "0111";
\counter[1]~134_pathsel\ <= "10111001";
\clk~I_modesel\ <= "00000000000000000000000001";
\clk~clkctrl_modesel\ <= '0';
\wrData[11]~I_modesel\ <= "00000000000000000000000001";
\wr_en~I_modesel\ <= "00000000000000000000000001";
\addr~I_modesel\ <= "00000000000000000000000001";
\duty[11]~411_modesel\ <= "1001";
\duty[11]~411_pathsel\ <= "00001100";
\counter[0]~133_modesel\ <= "1011";
\counter[0]~133_pathsel\ <= "01001010";
\wrData[0]~I_modesel\ <= "00000000000000000000000001";
\period[0]~feeder_modesel\ <= "1001";
\period[0]~feeder_pathsel\ <= "00001000";
\period[11]~404_modesel\ <= "1001";
\period[11]~404_pathsel\ <= "00001100";
\counter[8]~141_modesel\ <= "0111";
\counter[8]~141_pathsel\ <= "10111001";
\wrData[8]~I_modesel\ <= "00000000000000000000000001";
\period[8]~feeder_modesel\ <= "1001";
\period[8]~feeder_pathsel\ <= "00001000";
\counter[10]~143_modesel\ <= "0111";
\counter[10]~143_pathsel\ <= "11011010";
\counter[11]~132_modesel\ <= "0101";
\counter[11]~132_pathsel\ <= "00011000";
\Equal0~108_modesel\ <= "1001";
\Equal0~108_pathsel\ <= "00001111";
\counter[2]~135_modesel\ <= "0111";
\counter[2]~135_pathsel\ <= "10111001";
\wrData[2]~I_modesel\ <= "00000000000000000000000001";
\Equal0~110_modesel\ <= "1001";
\Equal0~110_pathsel\ <= "00001111";
\counter[6]~139_modesel\ <= "0111";
\counter[6]~139_pathsel\ <= "10111001";
\wrData[6]~I_modesel\ <= "00000000000000000000000001";
\period[6]~feeder_modesel\ <= "1001";
\period[6]~feeder_pathsel\ <= "00001000";
\Equal0~109_modesel\ <= "1001";
\Equal0~109_pathsel\ <= "00001111";
\Equal0~111_modesel\ <= "1001";
\Equal0~111_pathsel\ <= "00001110";
\counter[3]~136_modesel\ <= "0111";
\counter[3]~136_pathsel\ <= "11011010";
\wrData[3]~I_modesel\ <= "00000000000000000000000001";
\counter[4]~137_modesel\ <= "0111";
\counter[4]~137_pathsel\ <= "10111001";
\counter[5]~138_modesel\ <= "0111";
\counter[5]~138_pathsel\ <= "11011010";
\wrData[5]~I_modesel\ <= "00000000000000000000000001";
\period[5]~feeder_modesel\ <= "1001";
\period[5]~feeder_pathsel\ <= "00001000";
\counter[7]~140_modesel\ <= "0111";
\counter[7]~140_pathsel\ <= "11011010";
\wrData[7]~I_modesel\ <= "00000000000000000000000001";
\period[7]~feeder_modesel\ <= "1001";
\period[7]~feeder_pathsel\ <= "00001000";
\counter[9]~142_modesel\ <= "0111";
\counter[9]~142_pathsel\ <= "11011010";
\wrData[9]~I_modesel\ <= "00000000000000000000000001";
\period[9]~feeder_modesel\ <= "1001";
\period[9]~feeder_pathsel\ <= "00001000";
\wrData[10]~I_modesel\ <= "00000000000000000000000001";
\wrData[4]~I_modesel\ <= "00000000000000000000000001";
\wrData[1]~I_modesel\ <= "00000000000000000000000001";
\LessThan0~157_modesel\ <= "0110";
\LessThan0~157_pathsel\ <= "01100000";
\LessThan0~159_modesel\ <= "0110";
\LessThan0~159_pathsel\ <= "11100000";
\LessThan0~161_modesel\ <= "0110";
\LessThan0~161_pathsel\ <= "11100000";
\LessThan0~163_modesel\ <= "0110";
\LessThan0~163_pathsel\ <= "11100000";
\LessThan0~165_modesel\ <= "0110";
\LessThan0~165_pathsel\ <= "11100000";
\LessThan0~167_modesel\ <= "0110";
\LessThan0~167_pathsel\ <= "11100000";
\LessThan0~169_modesel\ <= "0110";
\LessThan0~169_pathsel\ <= "11100000";
\LessThan0~171_modesel\ <= "0110";
\LessThan0~171_pathsel\ <= "11100000";
\LessThan0~173_modesel\ <= "0110";
\LessThan0~173_pathsel\ <= "11100000";
\LessThan0~175_modesel\ <= "0110";
\LessThan0~175_pathsel\ <= "11100000";
\LessThan0~177_modesel\ <= "0110";
\LessThan0~177_pathsel\ <= "11100000";
\LessThan0~178_modesel\ <= "0101";
\LessThan0~178_pathsel\ <= "00011001";
\PwmOut~2_modesel\ <= "1001";
\PwmOut~2_pathsel\ <= "00001000";
\PwmOut~I_modesel\ <= "00000000000000000000000010";

\clk~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \clk~combout\);

-- atom is at LCFF_X25_Y8_N11
\counter[1]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \counter[1]~134_combout\,
	sdata => \period[1]~regout\,
	aclr => GND,
	sclr => GND,
	sload => \Equal0~111_combout\,
	ena => VCC,
	regout => \counter[1]~regout\);

-- atom is at LCCOMB_X25_Y8_N10
\counter[1]~134\ : cycloneii_lcell_comb
-- Equation(s):
-- \counter[1]~134_combout\ = \counter[1]~regout\ & \counter[0]~144\ & VCC # !\counter[1]~regout\ & !\counter[0]~144\
-- \counter[1]~145\ = CARRY(!\counter[1]~regout\ & !\counter[0]~144\)