new_pwm.map.rpt

一个PWM参数器

; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                               ;
+----------------------------------+-----------------+-----------------+-------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path  ;
+----------------------------------+-----------------+-----------------+-------------------------------+
; new_pwm.vhd                      ; yes             ; User VHDL File  ; E:/mywork/new_pwm/new_pwm.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 73    ;
;     -- Combinational with no register       ; 23    ;
;     -- Register only                        ; 32    ;
;     -- Combinational with a register        ; 18    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 5     ;
;     -- 3 input functions                    ; 16    ;
;     -- 2 input functions                    ; 18    ;
;     -- 1 input functions                    ; 2     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 43    ;
;     -- arithmetic mode                      ; 30    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 16    ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 50    ;
; Total logic cells in carry chains           ; 32    ;
; I/O pins                                    ; 37    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 50    ;
; Total fan-out                               ; 254   ;
; Average fan-out                             ; 2.31  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |new_pwm                   ; 73 (73)     ; 50           ; 0           ; 37   ; 0            ; 23 (23)      ; 32 (32)           ; 18 (18)          ; 32 (32)         ; 0 (0)      ; |new_pwm            ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 50    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 16    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 32    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/mywork/new_pwm/new_pwm.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Nov 15 10:18:41 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off new_pwm -c new_pwm
Info: Found 2 design units, including 1 entities, in source file new_pwm.vhd
    Info: Found design unit 1: new_pwm-one
    Info: Found entity 1: new_pwm
Info: Found 1 design units, including 1 entities, in source file load_control.bdf
    Info: Found entity 1: load_control
Info: Found 2 design units, including 1 entities, in source file ../counter_set/counter_set.vhd
    Info: Found design unit 1: counter_set-one
    Info: Found entity 1: counter_set
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Elaborating entity "new_pwm" for the top level hierarchy
Info: Implemented 110 device resources after synthesis - the final resource count might be different
    Info: Implemented 35 input pins
    Info: Implemented 2 output pins
    Info: Implemented 73 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 152 megabytes of memory during processing
    Info: Processing ended: Thu Nov 15 10:18:50 2007
    Info: Elapsed time: 00:00:09