📄 newone.vwf

📁 一个PWM参数器
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	DATA_OFFSET = 0.0;
	DATA_DURATION = 20000.0;
	SIMULATION_TIME = 0.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("wrData")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 16;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("wrData[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[10]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[11]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("wrData[15]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wrData";
}

SIGNAL("pwm_signal")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("wr_period")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 16;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("wr_period[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[10]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[11]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

SIGNAL("wr_period[15]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "wr_period";
}

TRANSITION_LIST("wrData[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		NODE
		{
			REPEAT = 997;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 10.0;
		}
	}
}

TRANSITION_LIST("wrData[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 20.0;
		NODE
		{
			REPEAT = 498;
			LEVEL 0 FOR 20.0;
			LEVEL 1 FOR 20.0;
		}
	}
}

TRANSITION_LIST("wrData[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 40.0;
		NODE
		{
			REPEAT = 249;
			LEVEL 0 FOR 40.0;
			LEVEL 1 FOR 40.0;
		}
	}
}

TRANSITION_LIST("wrData[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 80.0;
		LEVEL 1 FOR 80.0;
		NODE
		{
			REPEAT = 124;
			LEVEL 0 FOR 80.0;
			LEVEL 1 FOR 80.0;
		}
	}
}

TRANSITION_LIST("wrData[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 120.0;
		LEVEL 1 FOR 160.0;
		NODE
		{
			REPEAT = 61;
			LEVEL 0 FOR 160.0;
			LEVEL 1 FOR 160.0;
		}
		LEVEL 0 FOR 160.0;
	}
}

TRANSITION_LIST("wrData[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 320.0;
		NODE
		{
			REPEAT = 30;
			LEVEL 0 FOR 320.0;
			LEVEL 1 FOR 320.0;
		}
		LEVEL 0 FOR 160.0;
	}
}

TRANSITION_LIST("wrData[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 640.0;
		LEVEL 1 FOR 640.0;
		NODE
		{
			REPEAT = 14;
			LEVEL 0 FOR 640.0;
			LEVEL 1 FOR 640.0;
		}
		LEVEL 0 FOR 640.0;
		LEVEL 1 FOR 160.0;
	}
}

TRANSITION_LIST("wrData[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1280.0;
		LEVEL 1 FOR 1280.0;
		NODE
		{
			REPEAT = 6;
			LEVEL 0 FOR 1280.0;
			LEVEL 1 FOR 1280.0;
		}
		LEVEL 0 FOR 1280.0;
		LEVEL 1 FOR 800.0;
	}
}

TRANSITION_LIST("wrData[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2560.0;
		LEVEL 1 FOR 2560.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 2560.0;
			LEVEL 1 FOR 2560.0;
		}
		LEVEL 0 FOR 2560.0;
		LEVEL 1 FOR 2080.0;
	}
}

TRANSITION_LIST("wrData[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5120.0;
		LEVEL 1 FOR 5120.0;
		LEVEL 0 FOR 5120.0;
		LEVEL 1 FOR 4640.0;
	}
}

TRANSITION_LIST("wrData[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10240.0;
		LEVEL 1 FOR 9760.0;
	}
}

TRANSITION_LIST("wrData[11]")
{
	NODE
	{
12 下一页
💿 文件大小 227 K
👤 上传用户 qq569854
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#PWM #参数
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