tb_stop_watch.vhd

vhdl语言编写的一个秒表源码

use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.numeric_std.all;
use IEEE.std_logic_textio.all;


ENTITY tb_stop_watch IS

END tb_stop_watch ;

ARCHITECTURE behavioral_tb_stop_watch OF tb_stop_watch IS
  COMPONENT stop_watch
  port(
    CLK        : in std_logic;   --4096 Hz
    RESET      : in std_logic; 
    KEY1       : in std_logic; 
    KEY2       : in std_logic; 
    DISPL_1    : out    std_logic_vector (6 DOWNTO 0);
    DISPL_10   : out    std_logic_vector (6 DOWNTO 0);
    DISPL_100  : out    std_logic_vector (6 DOWNTO 0);
    DISPL_1000 : out    std_logic_vector (6 DOWNTO 0)
  );
  END COMPONENT;

  COMPONENT stop_watch_reference
  port(
    CLK        : in std_logic;   --4096 Hz
    RESET      : in std_logic; 
    KEY1       : in std_logic; 
    KEY2       : in std_logic; 
    DISPL_1    : out    std_logic_vector (6 DOWNTO 0);
    DISPL_10   : out    std_logic_vector (6 DOWNTO 0);
    DISPL_100  : out    std_logic_vector (6 DOWNTO 0);
    DISPL_1000 : out    std_logic_vector (6 DOWNTO 0)
  );
  END COMPONENT;

  signal  CLK        : std_logic := '0';   
  signal  RESET      : std_logic; 
  signal  KEY1       : std_logic:= '1'; 
  signal  KEY2       : std_logic:= '1'; 
  signal  DISPL_1    : std_logic_vector (6 DOWNTO 0);
  signal  DISPL_10   : std_logic_vector (6 DOWNTO 0);
  signal  DISPL_100  : std_logic_vector (6 DOWNTO 0);
  signal  DISPL_1000 : std_logic_vector (6 DOWNTO 0);
  signal  SIMEND        : std_logic := '0';   

  signal  DUMMY          : std_logic_vector (6 DOWNTO 0):= "1111110";
  signal  ZERO           : std_logic:= '0';
  signal  clkcounter     : integer :=0;
  signal  DISPL_1_REF    : std_logic_vector (6 DOWNTO 0);
  signal  DISPL_10_REF   : std_logic_vector (6 DOWNTO 0);
  signal  DISPL_100_REF  : std_logic_vector (6 DOWNTO 0);
  signal  DISPL_1000_REF : std_logic_vector (6 DOWNTO 0);
  
  signal DISPL_1_DEC: std_logic_vector(3 downto 0);
  signal DISPL_10_DEC: std_logic_vector(3 downto 0);
  signal DISPL_100_DEC: std_logic_vector(3 downto 0);
  signal DISPL_1000_DEC: std_logic_vector(3 downto 0);

  signal DISPL_1_REF_DEC: std_logic_vector(3 downto 0);
  signal DISPL_10_REF_DEC: std_logic_vector(3 downto 0);
  signal DISPL_100_REF_DEC: std_logic_vector(3 downto 0);
  signal DISPL_1000_REF_DEC: std_logic_vector(3 downto 0);
  
  constant CLKPERIOD: time := 0.24414 ms; -- frequency 4096 Hz
  
  function func_7seg_2_bcd(seg7: std_logic_vector(6 downto 0))
    return std_logic_vector is
    variable result: std_logic_vector(3 downto 0);
  begin
    case seg7 is
      when "1111110" =>
        result := "0000";
  	  when "1100000" =>
  	    result := "0001";
  	  when "1011011" =>
  	    result := "0010";
  	  when "1110011" =>
  	    result := "0011";
   	  when "1100101" =>
   	    result := "0100";
   	  when "0110111" =>
   	    result := "0101";
   	  when "0111111" =>
   	    result := "0110";
   	  when "1100010" =>
   	    result := "0111";
   	  when "1111111" =>
   	    result := "1000";
   	  when "1110111" =>
   	    result := "1001";
  	  when others =>
  	    result := "1110";
	  end case;
	  return result;
  end func_7seg_2_bcd;
  
BEGIN

  -----------------------------------------------------------------------------------
  --component unit under test: stop_watch
  UUT_STOP_WATCH : stop_watch
      PORT MAP (
         CLK       => CLK,
         RESET     => RESET,
         KEY1      => KEY1,
         KEY2      => KEY2,
         DISPL_1   => DISPL_1,
         DISPL_10   => DISPL_10,
         DISPL_100   => DISPL_100,
         DISPL_1000   => DISPL_1000
      );

  --reference component: stop_watch_reference
  REF_STOP_WATCH : stop_watch_reference
      PORT MAP (
         CLK       => CLK,
         RESET     => RESET,
         KEY1      => KEY1,
         KEY2      => KEY2,
         DISPL_1   => DISPL_1_REF,
         DISPL_10   => DISPL_10_REF,
         DISPL_100   => DISPL_100_REF,
         DISPL_1000   => DISPL_1000_REF
      );

  -----------------------------------------------------------------------------------
  --generate clock and reset signal
  CLK <= not CLK after CLKPERIOD/2 when SIMEND = '0' else '0';
  RESET <= '1', '0' after 1000000 ns;

  -----------------------------------------------------------------------------------
  --generate input signals and test for correct output signals
  process
  begin
    KEY1 <= '0';
    KEY2 <= '0';
    wait for 300 ms;
      KEY1 <= '1', '0' after 1 ms;
    wait for 300 ms;
      KEY2 <= '1', '0' after  1 ms;
      if (DISPL_1 = "1110111" AND DISPL_10 = "1011011") then
        assert(false)
        report "SIMULATION OK (INTERMEDIATE TIME)! "
        severity note;
      else  
        assert(false)
        report "SIMULATION ERROR (INTERMEDIATE TIME)! DISPL_1  should be 1110111 = 2; DISPL_10 should be 1011011 = 9 "
        severity warning;
      end if;
    wait for 100 ms;
      KEY2 <= '1', '0' after  1 ms;
    wait for 30 ms;
      KEY1 <= '1', '0' after  1 ms;
    wait for 120 ms;
      KEY1 <= '1', '0' after  1 ms;
    wait for 120 ms;
      KEY1 <= '1', '0' after  1 ms;
    wait for 400 ms;
      if (DISPL_1 = "1100101" AND DISPL_10 = "0110111") then
        assert(false)
        report "SIMULATION OK (STOP_TIME)! "
        severity note;
      else  
        assert(false)
        report "SIMULATION ERROR (STOP_TIME)! DISPL_1  should be 1100101 = 4; DISPL_10 should be 0110111 = 5 "
        severity warning;
      end if;
      KEY2 <= '1', '0' after  1 ms;
    wait for 10 ms;
      if (DISPL_1 = "1111110" AND DISPL_10 = "1111110") then
        assert(false)
        report "SIMULATION OK (START)! "
        severity note;
      else  
        assert(false)
        report "SIMULATION ERROR (START)! DISPL_1  should be 1111110 = 0; DISPL_10 should be 1111110 = 0 "
        severity warning;
      end if;
    wait for 30 ms;
      SIMEND <= '1';
     wait until SIMEND = '0';  -- Stop Simulation
  end process;

  -----------------------------------------------------------------------------------
  --convert 7seg to bcd
  DISPL_1_DEC <= func_7seg_2_bcd(DISPL_1);
  DISPL_10_DEC <= func_7seg_2_bcd(DISPL_10);
  DISPL_100_DEC <= func_7seg_2_bcd(DISPL_100);
  DISPL_1000_DEC <= func_7seg_2_bcd(DISPL_1000);
  DISPL_1_REF_DEC <= func_7seg_2_bcd(DISPL_1_REF);
  DISPL_10_REF_DEC <= func_7seg_2_bcd(DISPL_10_REF);
  DISPL_100_REF_DEC <= func_7seg_2_bcd(DISPL_100_REF);
  DISPL_1000_REF_DEC <= func_7seg_2_bcd(DISPL_1000_REF);

  -----------------------------------------------------------------------------------
  -- Logfile generation
  -- The signals from the reference unit and the students' unit are printed to one file (display.log). 
  -- Just log if the signals from the students Unit change
  process( DISPL_1, DISPL_10, DISPL_100, DISPL_1000, 
           DISPL_1_REF, DISPL_10_REF, DISPL_100_REF, DISPL_1000_REF )
    file logfile: text open write_mode is "display.log";
    variable lab_l1, ref_l1, spacer : line;
  begin
   
    write( lab_l1, string'("LAB ") );
    write( ref_l1, string'("REF ") );
  
    write( lab_l1, DUMMY );
    write( ref_l1, DUMMY );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, DUMMY );
    write( ref_l1, DUMMY );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, DISPL_1000 );
    write( ref_l1, DISPL_1000_REF );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, DISPL_100 );
    write( ref_l1, DISPL_100_REF );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, DISPL_10 );
    write( ref_l1, DISPL_10_REF );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, DISPL_1 );
    write( ref_l1, DISPL_1_REF );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, ZERO );
    write( ref_l1, ZERO );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, ZERO );
    write( ref_l1, ZERO );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, ZERO );
    write( ref_l1, ZERO );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, ZERO );
    write( ref_l1, ZERO );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, ZERO );
    write( ref_l1, ZERO );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, ZERO );
    write( ref_l1, ZERO );
    write( lab_l1, string'(" ") );
    write( ref_l1, string'(" ") );
  
    write( lab_l1, clkcounter );
    write( ref_l1, clkcounter );
  
    write( spacer, string'("") ); 
    writeline( logfile, lab_l1 );
    writeline( logfile, ref_l1 );
    writeline( logfile, spacer );
  
  end process;

  -- counter for clock cycles and seconds
  process
  begin
    wait until (clk'event and clk='1');
    wait until (clk'event and clk='1');
    clkcounter <= clkcounter + 1;
  end process;

END behavioral_tb_stop_watch;

configuration CFG_TB of tb_stop_watch is
   for behavioral_tb_stop_watch
   end for;
end CFG_TB;