disp_out.vhd

vhdl语言编写的一个秒表源码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY disp_out IS
  port(
    CLK        : in std_logic;   --4096 kHz
    DISP_HOLD  : in std_logic; 
    ENABLE_10MS   : in    std_logic;
    SET_ZERO   : in    std_logic;
    M_TIME     : in std_logic_vector(13 downto 0); 
    DISPL_1    : out    std_logic_vector (6 DOWNTO 0);
    DISPL_10   : out    std_logic_vector (6 DOWNTO 0);
    DISPL_100  : out    std_logic_vector (6 DOWNTO 0);
    DISPL_1000 : out    std_logic_vector (6 DOWNTO 0)
  );

END disp_out ;

-- hds interface_end
ARCHITECTURE behavioral_disp_out OF disp_out IS
  COMPONENT dual2bcd
  GENERIC (
     DUALBITS : natural := 14;
     BCDBITS  : natural := 16;
     BCDBLKS  : natural := 4
  );
  PORT (
     RESET  : IN     std_logic ;
     CLK    : IN     std_logic ;
     START  : IN     std_logic ;
     DUAL   : IN     std_logic_vector (DUALBITS-1 DOWNTO 0);
     BCD    : OUT    std_logic_vector (BCDBITS-1 DOWNTO 0);
     READY  : OUT    std_logic 
  );
  END COMPONENT;
  COMPONENT bcd_2_7seg
  PORT (
     BCD    : IN     std_logic_vector(3 downto 0);
     DISPL  : OUT    std_logic_vector(6 downto 0)
  );
  END COMPONENT;
  signal RESET :  std_logic;
  signal START_BCD :  std_logic;
  signal BCD_READY :  std_logic;
  signal BCD_SIGNAL_16 :  std_logic_vector(15 downto 0);
  signal BCD_SIGNAL_REG :  std_logic_vector(15 downto 0);
 BEGIN
   RESET <= SET_ZERO ;
   DUAL2BCD_MODULE : DUAL2BCD
      GENERIC MAP (
         DUALBITS => 14,
         BCDBITS  => 16,
         BCDBLKS  => 4
      )
      PORT MAP (
         RESET => RESET,
         CLK    => CLK,
         START  => START_BCD,
         DUAL   => M_TIME,
         BCD    => BCD_SIGNAL_16,
         READY  => BCD_READY
      );

  process(CLK)
  begin
   if CLK'event and CLK = '1' then
     if SET_ZERO = '1' then
       BCD_SIGNAL_REG <= (Others => '0');
     elsif DISP_HOLD = '0' and BCD_READY = '1' then
        BCD_SIGNAL_REG <= BCD_SIGNAL_16;
     end if;
   end if;
  end process;

  process(CLK)
  begin
   if CLK'event and CLK = '1' then
     if SET_ZERO = '1' then
       START_BCD <=  '0';
     else
       START_BCD <= ENABLE_10MS;
     end if;
   end if;
  end process;
 
   SEGM_1 : bcd_2_7seg
      PORT MAP (
         BCD => BCD_SIGNAL_REG(3 downto 0),
         DISPL    => DISPL_1
      );
   SEGM_10 : bcd_2_7seg
      PORT MAP (
         BCD => BCD_SIGNAL_REG(7 downto 4),
         DISPL    => DISPL_10
      );
   SEGM_100 : bcd_2_7seg
      PORT MAP (
         BCD => BCD_SIGNAL_REG(11 downto 8),
         DISPL    => DISPL_100
      );
   SEGM_1000 : bcd_2_7seg
      PORT MAP (
         BCD => BCD_SIGNAL_REG(15 downto 12),
         DISPL    => DISPL_1000
      );
 

END behavioral_disp_out;