control.vhd

vhdl语言编写的一个秒表源码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY control IS
  port(
    CLK        : in std_logic;   --4096 Hz
    RESET      : in std_logic; 
    KEY1       : in std_logic; 
    KEY2       : in std_logic; 
    DISP_HOLD  : out    std_logic;
    MEASURE    : out    std_logic;
    SET_ZERO   : out    std_logic
  );

END control ;

ARCHITECTURE behavioral_control OF control IS
  type T_STATE is (START, MEASURE_CONT, MEASURE_STOP,MEASURE_INTERM); 
  signal ACTUAL_STATE, NEXT_STATE : T_STATE;
  signal IN_DATA : std_logic_vector(1 downto 0);
begin
  IN_DATA(0) <= KEY1;
  IN_DATA(1) <= KEY2;

  STATE_TRANSITION_LOGIC: process (ACTUAL_STATE, IN_DATA)
  begin
    case ACTUAL_STATE is
      when START =>
        case IN_DATA is
          when "01" => NEXT_STATE <= MEASURE_CONT;
          when "10" => NEXT_STATE <= START;
          when "11" => NEXT_STATE <= MEASURE_CONT;
          when others => NEXT_STATE <= START;
        end case;
      when MEASURE_CONT =>
        case IN_DATA is
          when "01" => NEXT_STATE <= MEASURE_STOP;
          when "10" => NEXT_STATE <= MEASURE_INTERM;
          when "11" => NEXT_STATE <= MEASURE_STOP;
          when others => NEXT_STATE <= MEASURE_CONT;
        end case;
      when MEASURE_STOP =>
        case IN_DATA is
          when "01" => NEXT_STATE <= MEASURE_CONT;
          when "10" => NEXT_STATE <= START;
          when "11" => NEXT_STATE <= START;
          when others => NEXT_STATE <= MEASURE_STOP;
        end case;
      when MEASURE_INTERM =>
	case IN_DATA is
	  when "01" => NEXT_STATE <= MEASURE_STOP;
	  when "10" => NEXT_STATE <= MEASURE_CONT;
	  when "11" => NEXT_STATE <= MEASURE_STOP;
	  when others => NEXT_STATE <= MEASURE_INTERM;
	end case;
       when others => NEXT_STATE <= START;
      end case;
    end process; -- TRANSITION_STATE_LOGIC
    
    STATE_MEM: process (CLK)
    begin
      if (CLK'event and CLK = '1' ) then
        if (RESET = '1') then
          ACTUAL_STATE <= START;
        else
          ACTUAL_STATE <= NEXT_STATE;
        end if;
      end if;
    end process; -- STATE_MEM
    
    OUTPUT_LOGIC: process (ACTUAL_STATE)
    begin
      case ACTUAL_STATE is
        when START =>
          DISP_HOLD <= '0';
          MEASURE   <= '0';
          SET_ZERO  <= '1';
        when MEASURE_CONT =>
          DISP_HOLD <= '0';
          MEASURE   <= '1';
          SET_ZERO  <= '0';
        when MEASURE_STOP =>
          DISP_HOLD <= '0';
          MEASURE   <= '0';
          SET_ZERO  <= '0';
        when MEASURE_INTERM =>
          DISP_HOLD <= '1';
          MEASURE   <= '1';
          SET_ZERO  <= '0';
        end case;
      end process; -- OUTPUT_LOGIC
END behavioral_control;