stop_watch.vhd

vhdl语言编写的一个秒表源码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY stop_watch IS
  port(
    CLK        : in std_logic;   --4096 Hz
    RESET      : in std_logic;   -- LOW active
    KEY1       : in std_logic;   -- LOW active
    KEY2       : in std_logic;   -- LOW active
    DISPL_1    : out    std_logic_vector (6 DOWNTO 0);
    DISPL_10   : out    std_logic_vector (6 DOWNTO 0);
    DISPL_100  : out    std_logic_vector (6 DOWNTO 0);
    DISPL_1000 : out    std_logic_vector (6 DOWNTO 0)
  );

END stop_watch ;

ARCHITECTURE struct_stop_watch OF stop_watch IS
  signal DISP_HOLD   :  std_logic; 
  signal SET_ZERO    :  std_logic; 
  signal MEASURE     :  std_logic; 
  signal ENABLE_10MS :  std_logic; 
  signal M_TIME      :  std_logic_vector(13 downto 0); 
  signal OUTPUT_KEY1 :  std_logic; 
  signal OUTPUT_KEY2 :  std_logic; 

  COMPONENT control
  port(
    CLK        : in std_logic;   --2048 kHz
    RESET      : in std_logic; 
    KEY1       : in std_logic; 
    KEY2       : in std_logic; 
    DISP_HOLD  : out    std_logic;
    MEASURE    : out    std_logic;
    SET_ZERO   : out    std_logic
  );
  END COMPONENT;
  COMPONENT disp_out
  port(
    CLK        : in std_logic;   --2048 kHz
    DISP_HOLD  : in std_logic; 
    ENABLE_10MS   : in    std_logic;
    SET_ZERO   : in    std_logic;
    M_TIME     : in std_logic_vector(13 downto 0); 
    DISPL_1    : out    std_logic_vector (6 DOWNTO 0);
    DISPL_10   : out    std_logic_vector (6 DOWNTO 0);
    DISPL_100  : out    std_logic_vector (6 DOWNTO 0);
    DISPL_1000 : out    std_logic_vector (6 DOWNTO 0)
  );
  END COMPONENT;
  COMPONENT gen_10ms
  port(
    CLK        : in std_logic;   --2048 kHz
    SET_ZERO   : in std_logic; 
    ENABLE_10MS   : out    std_logic
  );
  END COMPONENT;
  COMPONENT time
  port(
    CLK         : in std_logic;   --2048 kHz
    ENABLE_10MS : in    std_logic;
    MEASURE     : in    std_logic;
    SET_ZERO    : in    std_logic;
    M_TIME      : out    std_logic_vector(13 downto 0)
  );
  END COMPONENT;
  COMPONENT pulse_shape
   PORT( 
      CLK        : IN     std_logic;
      KEY        : IN     std_logic;
      RESET      : IN     std_logic;
      OUTPUT_KEY : OUT    std_logic
   );
  END COMPONENT;

BEGIN
  CONTROLLER : CONTROL
      PORT MAP (
         CLK       => CLK,
         RESET     => RESET,
         KEY1      => OUTPUT_KEY1,
         KEY2      => OUTPUT_KEY2,
         DISP_HOLD => DISP_HOLD,
         MEASURE   => MEASURE,
         SET_ZERO  => SET_ZERO
      );
  DISPLAY_OUTPUT : disp_out
      PORT MAP (
         CLK        => CLK,
         DISP_HOLD  => DISP_HOLD,
         ENABLE_10MS  => ENABLE_10MS,
         SET_ZERO    => SET_ZERO,
         M_TIME     => M_TIME,
         DISPL_1    => DISPL_1,
         DISPL_10   => DISPL_10,
         DISPL_100  => DISPL_100,
         DISPL_1000 => DISPL_1000
      );
  GENERATE_10MS_ENABLE : gen_10ms
      PORT MAP (
         CLK         => CLK,
         SET_ZERO    => SET_ZERO,
         ENABLE_10MS => ENABLE_10MS
      );
  TIME_MEASURE_SIGNALMENT : time
      PORT MAP (
         CLK         => CLK,
         ENABLE_10MS => ENABLE_10MS,
         MEASURE     => MEASURE,
         SET_ZERO    => SET_ZERO,
         M_TIME      => M_TIME
      );  
  pulse_shape_key1 : pulse_shape
      PORT MAP (
         CLK         => CLK,
         KEY         => KEY1,
         RESET       => RESET,
         OUTPUT_KEY  => OUTPUT_KEY1
      );
  pulse_shape_key2 : pulse_shape
      PORT MAP (
         CLK         => CLK,
         KEY         => KEY2,
         RESET       => RESET,
         OUTPUT_KEY  => OUTPUT_KEY2
      );

END struct_stop_watch;