bcd_2_7seg.vhd

vhdl语言编写的一个秒表源码

-- hds header_start
--
-- VHDL Architecture STOP_WATCH.bcd_2_7seg.behavioral_bcd_2_7seg
--
-- Created:
--          by - wschleck.allget (andromeda.rz.uni-ulm.de)
--          at - 13:31:06 05/13/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1 (Build 143)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY bcd_2_7seg IS
  PORT (
     BCD    : IN     std_logic_vector(3 downto 0);
     DISPL  : OUT    std_logic_vector(6 downto 0)
  );
END bcd_2_7seg ;

-- hds interface_end
ARCHITECTURE behavioral_bcd_2_7seg OF bcd_2_7seg IS
BEGIN

process ( BCD)
  begin
  case BCD is
  	  when "0000" => DISPL <= "1111110";
  	  when "0001" => DISPL <= "1100000";
  	  when "0010" => DISPL <= "1011011";
	  when "0011" => DISPL <= "1110011";
 	  when "0100" => DISPL <= "1100101";
 	  when "0101" => DISPL <= "0110111";
 	  when "0110" => DISPL <= "0111111";
 	  when "0111" => DISPL <= "1100010";
 	  when "1000" => DISPL <= "1111111";
 	  when "1001" => DISPL <= "1110111";
	  when others => DISPL <= "0000001";
 end case;
 end process;
END behavioral_bcd_2_7seg;