pulse_shape.vhd

来自「vhdl语言编写的一个秒表源码」· VHDL 代码 · 共 42 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY pulse_shape IS
   PORT( 
      CLK        : IN     std_logic;
      KEY        : IN     std_logic;
      RESET      : IN     std_logic;
      OUTPUT_KEY : OUT    std_logic
   );

END pulse_shape ;

ARCHITECTURE behavioral_pulse_shape OF pulse_shape IS
   signal delay : std_logic_vector(2 downto 0);
BEGIN
  
  process (CLK)
  begin  -- process
    if CLK'event and CLK = '1' then  -- rising clock edge
      if RESET = '1' then                 -- synchronous reset 
        delay <= (others => '0');
      else
        delay <= delay(1 downto 0) & key;
      end if;
    end if;
  end process;

  process (CLK)
  begin  -- process
    if CLK'event and CLK = '0' then  -- falling clock edge
      if RESET = '1' then                 -- synchronous reset 
        OUTPUT_KEY <= '0';
      else
        OUTPUT_KEY <= (  delay(1)) and ( not delay(2));
      end if;
    end if;
  end process;
END behavioral_pulse_shape;