clock.vhd

基于vhdl的数字钟 有闹钟,秒表,时钟,日期等功能 秒表可以开始,暂停,清零, 时钟可以设置时间, 还可以设置日期

    co1 <= s1;
    co2 <= s2; 
END wav; 
-------------------=============================----------------------=================
--               =================时钟和日期===================
--======================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY time IS
    PORT (clk,min,rst,day,hour,mon : IN STD_LOGIC;
               co1,co2,co3,co4,co5,co6,co7,co8,co9,co01 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END time;

ARCHITECTURE show OF time IS

   component cnt60co 
     PORT (clk : IN STD_LOGIC;
               ca : OUT STD_LOGIC;
               co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
    end component;

    component cnt24 
     PORT (clk : IN STD_LOGIC;
               ca : OUT STD_LOGIC;
               co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
    end component;

    component dy 
     PORT (clk,rst : IN STD_LOGIC;
              mon : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
              ca : OUT STD_LOGIC;
              co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
    end component;
    
    component mn
     PORT (clk,rst : IN STD_LOGIC;
              co1,co2,co3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
    end component;

    SIGNAL s1,s2,s3,s4,S5,S6,s7,s8,s9,s10,month: STD_LOGIC_VECTOR(3 DOWNTO 0);
    signal c1,c2,c3,c4,clkc1,clkc2,clkc3,clkc4,clkc5,clkc6,clkc7: std_logic;

    BEGIN
        u1:cnt60co port map(clk=>clk,co1=>s1,co2=>s2,ca=>c1);

        clkc1<= c1 OR min;

        u2:cnt60co port map(clk=>clkc1,co1=>s3,co2=>s4,ca=>c2);

        PROCESS (clk)
           BEGIN
             IF RISING_EDGE(clk) THEN
                 IF min='1' THEN clkc2<='0';
                 ELSE clkc2<=c2;
                 END IF;
             END IF;
        END PROCESS;

        clkc3<=clkc2 OR hour;

        u3:cnt24 port map(clk=>clkc3,co1=>s5,co2=>s6,ca=>c3);

        PROCESS (clk)
          BEGIN
             IF RISING_EDGE(clk) THEN
                 IF hour='1' THEN clkc4<='0';
                 ELSE clkc4<=c3;
                 END IF;
             END IF;
        END PROCESS;
 
       clkc5 <= clkc4 OR day ;

       U4:dy port map(clk=>clkc5,rst=>rst,mon=>month,co1=>s7,co2=>s8,ca=>c4);
       
       PROCESS (clk)
          BEGIN
             IF RISING_EDGE(clk) THEN
                 IF day='1' THEN clkc6<='0';
                 ELSE clkc6<=c4;
                 END IF;
             END IF;
        END PROCESS;
    
       clkc7<=clkc6 OR mon;
 
       u5:mn port map(clk=>clkc7,rst=>rst,co1=>s9,co2=>s10,co3=>month); 
        co1<=s1;
        co2<=s2;
        co3<=s3;
        co4<=s4;
        co5<=s5;
        co6<=s6;
        co7<=s7;
        co8<=s8;
        co9<=s9;
        co01<=s10;
end show;
-------------------=========================----------------------===================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt60co IS
    PORT (clk : IN STD_LOGIC;
             ca : OUT STD_LOGIC;
             co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cnt60co;
ARCHITECTURE wav OF cnt60co IS
     SIGNAL s1,s2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
     SIGNAL c : STD_LOGIC;
        BEGIN
            PROCESS (clk)
                BEGIN
                    IF RISING_EDGE(clk)  THEN
                          IF (s1 = 9) AND (s2 = 5)  THEN  
                             s1 <= "0000";
                             s2 <= "0000";
                             c <= '1';
                           ELSIF (s1 = 9)  THEN
                              s1 <= "0000";
                              s2 <= s2 + 1;
                              c <='0';
                           ELSE s1 <= s1 + 1;
                                c <= '0';
                           END IF;         
                    END IF;
            END PROCESS;
    co1 <= s1;
    co2 <= s2; 
    ca <= c;
END wav; 
------------------========================------------------=====================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt24 IS
    PORT (clk : IN STD_LOGIC;
             ca : OUT STD_LOGIC;
             co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cnt24;
ARCHITECTURE wav OF cnt24 IS
     SIGNAL s1,s2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
     SIGNAL c : STD_LOGIC;
        BEGIN
            PROCESS (clk)
                BEGIN
                  IF RISING_EDGE(clk)  THEN
                           IF (s1 = 3) AND (s2 = 2)  THEN  
                             s1 <= "0000";
                             s2 <= "0000";
                             c <= '1';
                           ELSIF (s1 = 9)  THEN
                              s1 <= "0000";
                              s2 <= s2 + 1;
                              c <= '0';
                           ELSE s1 <= s1 + 1;
                                c <= '0';
                           END IF;  
                   END IF;
            END PROCESS;
    co1 <= s1;
    co2 <= s2; 
    ca <= c;
END wav; 

-------------------------============================--------------------===============
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dy IS
    PORT (clk,rst : IN STD_LOGIC;
              mon : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
              ca : OUT STD_LOGIC;
              co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END dy;
ARCHITECTURE grw OF dy IS
    SIGNAL s1,s2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL c : STD_LOGIC;
    BEGIN
        PROCESS (clk,rst,mon)
           BEGIN
             IF rst = '1' THEN 
                     s1 <= "0001";
                     s2 <= "0000";
             ELSIF RISING_EDGE(clk)  THEN
                     IF (mon = "0001")OR(mon="0011")OR(mon="0101")OR(mon="0111")OR(mon="1000")OR(mon="1010")OR(mon="1100") THEN
                         IF s1=1 AND s2=3  THEN
                             s2 <= "0000" ;
                             c <= '1' ;
                         ELSIF s1 = 9 THEN
                             s1 <= "0000";
                             s2 <= s2 + 1;
                             c <= '0';
                         ELSE s1 <= s1 + 1;
                             c <= '0';
                         END IF;

                     ELSIF (mon = "0100") OR (mon = "0110") OR(mon = "1001")OR(mon="1011") THEN
                         IF s1 = 0 AND s2=3 THEN
                            s1 <= s1 + 1 ;
                            s2 <= "0000";
                            c <= '1';
                         ELSIF  s1 = 9 THEN
                             s1 <= "0000";
                             s2 <= s2 + 1;
                             c <= '0';
                         ELSE s1 <= s1 + 1;
                             c<= '0';
                         END IF;

                     ELSIF mon = 2 THEN
                        IF s1=8 AND s2=2 THEN 
                            s1 <= "0001";
                            s2 <= "0000";
                            c <= '1';
                        ELSIF s1 = 9 THEN
                          s1 <= "0000";
                          s2 <= s2 + 1;
                             c <= '0';
                        ELSE s1 <= s1 + 1;
                           c <= '0';
                        END IF;
                      ELSE
                        s1<="0000";
                        s2<="0000";
                        c<='0';
                     END IF;
            END IF;
        END PROCESS;
     ca <= c;
     co1 <= s1;
     co2 <= s2;
END grw; 
            
---------------------------======================----------------------==================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mn IS
    PORT (clk,rst : IN STD_LOGIC;
              co1,co2,co3 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END mn;
ARCHITECTURE grw OF mn IS
    SIGNAL s1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL s2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL s3 : STD_LOGIC_VECTOR(3 DOWNTO 0);
    BEGIN
        PROCESS (clk,rst)
          BEGIN
             IF rst = '1' THEN 
                    s1 <="0001";
                    s2 <= "0000" ;
                    s3<= "0001";
             ELSIF RISING_EDGE(clk)  THEN
                    IF s1 = 2 AND s2 = 1  THEN
                             s1 <="0001";
                             s2 <= "0000" ;
                             s3<= "0001";
                    ELSIF s1 = 9 THEN
                             s1 <= "0000";
                             s2 <= s2 + 1;
                             s3 <= s3 + 1;
                   ELSE s1 <= s1 + 1; s3 <=s3 + 1;
                   END IF;
             END IF;
         END PROCESS;
    co1 <= s1;
    co2 <=s2;
    co3 <=s3;
END grw;
----------------------==================================-------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY nosy IS
   PORT(scmin,schour :IN STD_LOGIC;
        co1,co2,co3,co4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END nosy;
ARCHITECTURE behav OF nosy IS
component cnt60oo 
      PORT (clk : IN STD_LOGIC;
            co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
    end component;
COMPONENT cnt24o
    port(clk : IN STD_LOGIC;
         co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
    SIGNAL s1,s2,s3,s4 : STD_LOGIC_VECTOR(3 DOWNTO 0);
    BEGIN
         U1:cnt60oo PORT MAP(clk=>scmin, co1=>s1,co2=>s2);
         U2:cnt24o  PORT MAP(clk=>schour,co1=>s3,co2=>s4);
         co1<=s1;
         co2<=s2;
         co3<=s3;
         co4<=s4;
END behav;
---------==========================---------------============================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt60oo IS
    PORT (clk : IN STD_LOGIC;
             co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cnt60oo;
ARCHITECTURE wav OF cnt60oo IS
     SIGNAL s1,s2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
        BEGIN
            PROCESS (clk)
                BEGIN
                    IF RISING_EDGE(clk)  THEN
                          IF (s1 = 9) AND (s2 = 5)  THEN  
                             s1 <= "0000";
                             s2 <= "0000";
                           ELSIF (s1 = 9)  THEN
                              s1 <= "0000";
                              s2 <= s2 + 1;
                           ELSE s1 <= s1 + 1;
                           END IF;         
                    END IF;
            END PROCESS;
    co1 <= s1;
    co2 <= s2; 
END wav; 
------------------========================------------------================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt24o IS
    PORT (clk : IN STD_LOGIC;
             co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cnt24o;
ARCHITECTURE wav OF cnt24o IS
     SIGNAL s1,s2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
        BEGIN
            PROCESS (clk)
                BEGIN
                  IF RISING_EDGE(clk)  THEN
                           IF (s1 = 3) AND (s2 = 2)  THEN  
                             s1 <= "0000";
                             s2 <= "0000";
                           ELSIF (s1 = 9)  THEN
                              s1 <= "0000";
                              s2 <= s2 + 1;
                           ELSE s1 <= s1 + 1;
                           END IF;  
                   END IF;
            END PROCESS;
    co1 <= s1;
    co2 <= s2; 
END wav; 

-------------------------============================--------------------================